Z synchronous data timing – Rainbow Electronics BR24L01AFVM-W User Manual
Page 6
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zSynchronous data timing
t
BUF
t
PD
t
HIGH
t
HD :
STA
t
LOW
t
F
t
R
SCL
START BIT
STOP BIT
SCL
SDA
t
DH
t
SU
: DAT
t
HD
: DAT
t
SU
: STO
t
HD
: STA
t
SU
: STA
SDA
(OUT)
SDA
(IN)
Fig.4 SYNCHRONOUS DATA TIMING
•
SDA data is latched into the chip at the rising edge of SCL clock.
•
Output data toggles at the falling edge of SCL clock.
zWrite cycle timing
ACK
D0
t
WR
SDA
SCL
START CONDITION
STOP CONDITION
WRITE DATA (n)
Fig.5 WRITE CYCLE TIMING
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