Rainbow Electronics AT45DB041D - Manual (Page 38)

38
3595R–DFLASH–11/2012
AT45DB041D
21.6 Reset Timing
Note: The CS signal should be in the high state before the RESET signal is deasserted.
21.7 Command Sequence for Read/Write Operations for Page Size 256-Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
21.8 Command Sequence for Read/Write Operations for Page Size 264-Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
CS
SCK
RESET
SO (OUTPUT)
HIGH IMPEDANCE HIGH IMPEDANCE
SI (INPUT)
tRST
tREC tCSS
SI (INPUT) CMD 8 bits 8 bits 8 bits
Page Address
(A17 - A8)
X X X X X X X X X X X X X X X X LSB X X X X X X X X
Byte/Buffer Address
(A7 - A0/BFA7 - BFA0)
MSB
6 Don’t Care
Bits
Page Address
(PA9 - PA0)
Byte/Buffer Address
(BA8 - BA0/BFA8 - BFA0)
SI (INPUT) CMD 8-bits 8-bits 8-bits
X X X X X X X X X X X X LSB X X X X X X X X MSB
5 Don’t Care
Bits
X X X X