Rainbow Electronics AT89C5131 - Manual (Page 111)

111
AT89C5131
4136A–USB–03/03
Reset Value = 0001 0100b
Not bit addressable
Serial Peripheral Status
Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions:
• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error)
Table 79 describes the SPSTA register and explains the use of every bit in the register.
Table 79. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
2 SPR1
SPR2 SPR1 SPR0 Serial Peripheral Rate
0 0 0 Invalid
0 0 1 F
CLK PERIPH/
4
0 1 0 F
CLK PERIPH/
8
0 1 1 F
CLK PERIPH/
16
1 0 0 F
CLK PERIPH/
32
1 0 1 F
CLK PERIPH/
64
1 1 0 F
CLK PERIPH/
128
1 1 1 Invalid
1 SPR0
Bit
Number Bit Mnemonic Description
7 6 5 4 3 2 1 0
SPIF WCOL SSERR MODF - - - -
Bit
Number
Bit
Mnemonic Description
7 SPIF
Serial Peripheral data transfer flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
6 WCOL
Write Collision flag
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5 SSERR
Synchronous Serial Slave Error flag
Set by hardware when SS is de-
asserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4 MODF
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit