Power-up/power-down characteristics, Figure 1. power-up/power-down timing – Rainbow Electronics DS1338 User Manual

Page 4

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DS1338 I

2

C RTC with 56-Byte NV RAM

4 of 15

POWER-UP/POWER-DOWN CHARACTERISTICS

(T

A

= -40°C to +85°C) (Note 1, Figure 1)

PARAMETER SYMBOL

MIN

TYP

MAX

UNITS

Recovery at Power-Up (Note 15)

t

REC

2

ms

V

CC

Fall Time; V

PF(MAX)

to V

PF(MIN)

t

VCCF

300

ms

V

CC

Rise Time; V

PF(MIN)

to V

PF(MAX)

t

VCCR

0

ms


Note 1:

Limits at -40°C are guaranteed by design and not production tested.

Note 2:

All voltages are referenced to ground.

Note 3:

SCL only.

Note 4:

SDA and SQW/OUT.

Note 5:

I

CCA

—SCL clocking at max frequency = 400kHz.

Note 6:

Specified with the I

2

C bus inactive.

Note 7:

Measured with a 32.768kHz crystal attached to X1 and X2.

Note 8:

After this period, the first clock pulse is generated.

Note 9:

A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V

IHMIN

of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

Note 10:

The maximum t

HD:DAT

need only be met if the device does not stretch the LOW period (t

LOW

) of the SCL signal.

Note 11:

A fast-mode device can be used in a standard-mode system, but the requirement t

SU:DAT

≥ to 250ns must then be met. This is

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t

R MAX

+ t

SU:DAT

= 1000 + 250 = 1250ns before the SCL line

is released.

Note 12:

C

B

—total capacitance of one bus line in pF.

Note 13:

Guaranteed by design. Not production tested.

Note 14:

The parameter t

OSF

is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of

0.0V ≤ V

CC

≤ V

CC MAX

and 1.3V ≤ V

BAT

≤ 3.7V.

Note 15:

This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.



Figure 1. Power-Up/Power-Down Timing


OUTPUTS

V

CC

V

PF(max)

V

PF(min)

INPUTS

HIGH-Z

DON'T CARE

VALID

RECOGNIZED

RECOGNIZED

VALID

t

VCCF

t

VCCR

t

REC

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