Clock accuracy, Rtc and ram address map, Ds1338c only – Rainbow Electronics DS1338 User Manual

Page 9: Figure 5. typical pc board layout for crystal

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DS1338 I

2

C RTC with 56-Byte NV RAM

9 of 15

CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal
frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the
oscillator circuit can result in the clock running fast. Figure 5 shows a typical PC board layout for isolating the
crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks
for detailed information.

DS1338C ONLY

The DS1338C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal V

CC

and +25°C

is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.

Figure 5. Typical PC Board Layout for Crystal
























RTC AND RAM ADDRESS MAP

Figure 6 shows the address map for the RTC and RAM registers. The RTC registers and control register are
located in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a
multibyte access, when the register pointer reaches 3Fh (the end of RAM space) it wraps around to location 00h
(the beginning of the clock space). On an I

2

C START, STOP, or register pointer incrementing to location 00h, the

current time and date is transferred to a second set of registers. The time and date in the secondary registers are
read in a multibyte data transfer, while the clock continues to run. This eliminates the need to re-read the registers
in case of an update of the main registers during a read.

LOCAL GROUND PLANE (LAYER 2)

CRYSTAL

X1

X2

GND

NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED
AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE

UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL
LINE AND THE PACKAGE.

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