Document Outline

• Features
• Pin Configurations
• Description
• Block Diagram
• Pin Descriptions
  • VCC
  • GND
  • Port A (PA7..PA0)
  • Port B (PB7..PB0)
  • Port C (PC7..PC0)
  • Port D (PD7..PD0)
  • RESET
  • XTAL1
  • XTAL2
  • AVCC
  • AREF
  • AGND
  • Clock Options
    • Internal RC Oscillator
    • Crystal Oscillator
    • External Clock
    • External RC Oscillator
  • Timer Oscillator
• Architectural Overview
  • The General Purpose Register File
    • The X-register, Y-register, And Z-register
  • The ALU - Arithmetic Logic Unit
  • The In-System Self-programmable Flash Program Memory
  • The SRAM Data Memory
  • The Program and Data Addressing Modes
    • Register Direct, Single Register Rd
    • Register Direct, Two Registers Rd And Rr
    • I/O Direct
    • Data Direct
    • Data Indirect With Displacement
    • Data Indirect
    • Data Indirect With Pre-decrement
    • Data Indirect With Post-increment
    • Constant Addressing Using The LPM and SPM Instructions
    • Indirect Program Addressing, IJMP and ICALL
    • Relative Program Addressing, RJMP and RCALL
  • The EEPROM Data Memory
  • Memory Access Times and Instruction Execution Timing
  • I/O Memory
    • The Status Register - SREG
    • The Stack Pointer - SP
  • Reset and Interrupt Handling
    • Reset Sources
    • Power-on Reset
    • External Reset
    • Brown-out Detection
    • Watchdog Reset
    • MCU Status Register - MCUSR
    • Internal Voltage Reference
    • Voltage Reference Enable Signals and Start-up Time
    • Interrupt Handling
    • Interrupt Response Time
    • The General Interrupt Mask Register - GIMSK
    • The General Interrupt Flag Register - GIFR
    • The Timer/Counter Interrupt Mask Register - TIMSK
    • The Timer/Counter Interrupt Flag Register - TIFR
    • External Interrupts
    • MCU Control Register - MCUCR
  • Sleep Modes
    • Idle Mode
    • ADC Noise Reduction Mode
    • Power-down Mode
    • Power Save Mode
  • Calibrated Internal RC Oscillator
    • Oscillator Calibration Register - OSCCAL
    • Special Function IO Register - SFIOR
• Timer / Counters
  • Timer/Counter Prescalers
  • 8-bit Timer/Counter0
    • Timer/Counter0 Control Register - TCCR0
    • Timer/Counter 0 - TCNT0
  • 16-bit Timer/Counter1
    • Timer/Counter1 Control Register A - TCCR1A
    • Timer/Counter1 Control Register B - TCCR1B
    • Timer/Counter1 - TCNT1H and TCNT1L
    • TCNT1 Timer/Counter1 Write:
    • TCNT1 Timer/Counter1 Read:
    • Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
    • Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
    • Timer/Counter1 Input Capture Register - ICR1H and ICR1L
    • Timer/Counter1 in PWM Mode
  • 8-Bit Timer/Counter 2
    • Timer/Counter2 Control Register - TCCR2
    • Timer/Counter2 - TCNT2
    • Timer/Counter2 Output Compare Register - OCR2
    • Timer/Counter2 in PWM Mode
    • PWM Modes (Up/Down and Overflow)
    • Asynchronous Status Register - ASSR
    • Asynchronous Operation of Timer/Counter2
• Watchdog Timer
  • The Watchdog Timer Control Register - WDTCR
• EEPROM Read/Write Access
  • The EEPROM Address Register - EEARH and EEARL
  • The EEPROM Data Register - EEDR
  • The EEPROM Control Register - EECR
  • Preventing EEPROM Corruption
• Serial Peripheral Interface - SPI
  • SS Pin Functionality
  • Data Modes
    • SPI Control Register - SPCR
    • The SPI Status Register - SPSR
    • The SPI Data Register - SPDR
• UART
  • Data Transmission
  • Data Reception
    • Multi-processor Communication Mode
  • UART Control
    • UART I/O Data Register - UDR
    • UART Control and Status Register A - UCSRA
    • UART Control and Status Register B - UCSRB
    • Baud Rate Generator
    • UART Baud Rate Registers - UBRR and UBRRHI
  • Double Speed Transmission
    • The Baud Rate Generator in Double UART Speed Mode
• 2-wire Serial Interface (Byte Oriented)
  • The 2-wire Serial Interface Bit Rate Register - TWBR
  • The 2-wire Serial Interface Control Register - TWCR
  • The 2-wire Serial Interface Status Register - TWSR
  • The 2-wire Serial Interface Data Register - TWDR
  • The 2-wire Serial Interface (Slave) Address Register - TWAR
  • 2-wire Serial Interface Modes
  • Master Transmitter Mode
  • Master Receiver Mode
  • Slave Receiver Mode
  • Slave Transmitter Mode
  • Miscellaneous States
    • Assembly Code Example - Master Transmitter Mode
    • Assembly Code Example - Master Receiver Mode
    • Assembly Code Example - Slave Receiver Mode
    • Assembly Code Example - Slave Transmitter Mode
    • TWI Include File
• The Analog Comparator
  • The Analog Comparator Control And Status Register - ACSR
  • Analog Comparator Multiplexed Input
• Analog to Digital Converter
  • Feature List:
  • Operation
  • Prescaling and Conversion Timing
  • ADC Noise Canceler Function
    • The ADC Multiplexer Selection Register - ADMUX
    • The ADC Control and Status Register - ADCSR
    • The ADC Data Register - ADCL and ADCH
  • Scanning Multiple Channels
  • ADC Noise Canceling Techniques
• I/O-Ports
  • Port A
    • The Port A Data Register - PORTA
    • The Port A Data Direction Register - DDRA
    • The Port A Input Pins Address - PINA
    • PORT A as General Digital I/O
    • PORT A Schematics
  • Port B
    • The Port B Data Register - PORTB
    • The Port B Data Direction Register - DDRB
    • The Port B Input Pins Address - PINB
    • Port B As General Digital I/O
    • Alternate Functions Of PORTB
    • Port B Schematics
  • Port C
    • The Port C Data Register - PORTC
    • The Port C Data Direction Register - DDRC
    • The Port C Input Pins Address - PINC
    • Port C As General Digital I/O
    • Alternate Functions of PORTC
    • Port C Schematics
  • Port D
    • The Port D Data Register - PORTD
    • The Port D Data Direction Register - DDRD
    • The Port D Input Pins Address - PIND
    • Port D As General Digital I/O
    • Alternate Functions Of PORTD
    • Port D Schematics
• Memory Programming
  • Boot Loader Support
    • Entering the Boot Loader Program
    • Capabilities of the Boot Loader
  • Self-programming the Flash
    • Performing Page Erase by SPM
    • Fill the Temporary Buffer (Page Load)
    • Perform a Page Write
    • Consideration while Updating BLS
    • Wait for SPM Instruction to Complete
    • Instruction Word Read after Page Erase, Page Write, and Lock-bit Write
    • Avoid Reading the Application Section During Self-programming
    • Boot Loader Lock-bits
    • Setting the Boot Loader Lock Bits by SPM
    • Reading the Fuse and Lock Bits from Software
    • EEPROM Write Prevents Writing to SPMCR
    • Addressing the Flash During Self-programming
    • Store Program Memory Control Register - SPMCR
  • Preventing Flash Corruption
    • Assembly code example for a Boot Loader
  • Program And Data Memory Lock Bits
  • Fuse Bits
  • Signature Bytes
  • Calibration Byte
  • Parallel Programming
    • Signal Names
    • Enter Programming Mode
    • Chip Erase
    • Programming the Flash
    • Programming the EEPROM
    • Reading the Flash
    • Reading the EEPROM
    • Programming the Fuse Low Bits
    • Programming the Fuse High Bits
    • Programming the Lock Bits
    • Reading the Fuse and Lock Bits
    • Reading the Signature Bytes
    • Reading the Calibration Byte
  • Parallel Programming Characteristics
  • Serial Downloading
    • Serial Programming Algorithm
    • Data Polling Flash
    • Data Polling EEPROM
    • Programming Times for Non-Volatile Memory
  • Serial Programming Characteristics
• Electrical Characteristics
  • Absolute Maximum Ratings*
• DC Characteristics
• External Clock Drive Waveforms
• External Clock Drive
• 2-wire Serial Interface Characteristics
• Typical Characteristics - Preliminary Data
• Register Summary 
• Instruction Set Summary
• Ordering Information