Rainbow Electronics AT25640A - Manual (Page 5)

5
AT25080A/160A/320A/640A
3401C–SEEPR–8/04
Serial Interface
Description
MASTER: The device that generates the serial clock.
S L AV E : B e c a u s e t h e S e r i a l C l o c k p i n ( S C K ) i s a l w a y s a n i n p u t , t h e
AT25080A/160A/320A/640A always operates as a slave.
TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated
for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance
state until the falling edge of CS is detected agai n. This will reinitialize the serial
communication.
CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS pin is low. When
the device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
H O L D : T h e H O L D p i n i s u s e d i n c o n j u n c t i o n w i t h t h e C S p i n t o s e l e c t t h e
AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without resetting
the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low.
To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK
may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the
high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when
held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta-
tus register are inhibited. WP going low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been initiated, WP going low will have no effect
on any write operation to the status register. The WP pin function is blocked when the WPEN
bi t i n th e sta tus reg is te r i s "0 ". T hi s wi l l a ll ow the us er to i nsta ll the AT 25 08 0A/
160A/320A/640A in a system with the WP pin tied to ground and still be able to write to the
status register. All WP pin functions are enabled when the WPEN bit is set to “1”.