Document Outline

• TABLE OF CONTENTS
  • LIST OF FIGURES
  • LIST OF TABLES
• 1. DETAILED DESCRIPTION
• 2. FEATURE HIGHLIGHTS
  • 2.1 General
  • 2.2 Line Interface
  • 2.3 Clock Synthesizers
  • 2.4 Jitter Attenuator
  • 2.5 Framer/Formatter
  • 2.6 System Interface
  • 2.7 HDCL Controllers
  • 2.8 Test and Diagnostics
  • 2.9 Microcontroller Parallel Port
  • 2.10 Slave Serial Peripheral Interface (SPI) Features
• 3. APPLICATIONS
• 4. SPECIFICATIONS COMPLIANCE
• 5. ACRONYMS AND GLOSSARY
• 6. MAJOR OPERATING MODES
• 7. BLOCK DIAGRAMS
• 8. PIN DESCRIPTIONS
  • 8.1 Pin Functional Description
• 9. FUNCTIONAL DESCRIPTION
  • 9.1 Processor Interface
    • 9.1.1 SPI Serial Port Mode
    • 9.1.2 SPI Functional Timing Diagrams
      • 9.1.2.1 SPI Transmission Format and CPHA Polarity
  • 9.2 Clock Structure
    • 9.2.1 Backplane Clock Generation
    • 9.2.2 CLKO Output Clock Generation
  • 9.3 Resets and Power-Down Modes
  • 9.4 Initialization and Configuration
    • 9.4.1 Example Device Initialization and Sequence
  • 9.5 Global Resources
    • 9.5.1 General-Purpose I/O Pins
  • 9.6 Per-Port Resources
  • 9.7 Device Interrupts
  • 9.8 System Backplane Interface
    • 9.8.1 Elastic Stores
      • 9.8.1.1 Elastic Stores Initialization
      • 9.8.1.2 Minimum Delay Mode
      • 9.8.1.3 Additional Receive Elastic Store Information
      • 9.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane
      • 9.8.1.5 Mapping T1 Channels onto a 2.048MHz Backplane
      • 9.8.1.6 Receiving Mapped E1 Transmit Channels from a 1.544MHz Backplane
      • 9.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane
    • 9.8.2 IBO Multiplexing
    • 9.8.3 H.100 (CT Bus) Compatibility
    • 9.8.4 Transmit and Receive Channel Blocking Registers
    • 9.8.5 Transmit Fractional Support (Gapped Clock Mode)
    • 9.8.6 Receive Fractional Support (Gapped Clock Mode)
  • 9.9 Framers
    • 9.9.1 T1 Framing
    • 9.9.2 E1 Framing
    • 9.9.3 T1 Transmit Synchronizer
    • 9.9.4 Signaling
      • 9.9.4.1 Transmit-Signaling Operation
        • 9.9.4.1.1 Processor-Based Transmit Signaling
        • 9.9.4.1.2 Time Slot Numbering Schemes
      • TS
        • 9.9.4.1.3 Hardware-Based Transmit Signaling
      • 9.9.4.2 Receive-Signaling Operation
        • 9.9.4.2.1 Processor-Based Receive Signaling
        • 9.9.4.2.2 Change of State
        • 9.9.4.2.3 Hardware-Based Receive Signaling
        • 9.9.4.2.4 Receive-Signaling Reinsertion at RSERn
        • 9.9.4.2.5 Force Receive-Signaling All Ones
        • 9.9.4.2.6 Receive-Signaling Freeze
      • 9.9.4.3 Transmit SLC-96 Operation (T1 Mode Only)
      • 9.9.4.4 Receive SLC-96 Operation (T1 Mode Only)
    • 9.9.5 T1 Data Link
      • 9.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller
        • 9.9.5.1.1 To Transmit a BOC
      • 9.9.5.2 Receive Bit-Oriented Code (BOC) Controller
      • 9.9.5.3 Legacy T1 Transmit FDL
      • 9.9.5.4 Legacy T1 Receive FDL
    • 9.9.6 E1 Data Link
      • 9.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode)
        • 9.9.6.1.1 Internal Register Scheme Based on Double-Frame (Method 1)
        • 9.9.6.1.2 Internal Register Scheme Based on CRC-4 Multiframe (Receive)
        • 9.9.6.1.3 Internal Register Scheme Based on CRC-4 Multiframe (Transmit)
      • 9.9.6.2 Sa-Bit Monitoring and Reporting
    • 9.9.7 Maintenance and Alarms
      • 9.9.7.1 Status and Information Bit Operation
        • 9.9.7.1.1 Real-Time Bits
        • 9.9.7.1.2 Latched Bits
        • 9.9.7.1.3 Mask Bits
    • 9.9.8 Alarms
      • 9.9.8.1 Transmit RAI
      • 9.9.8.2 Receive RAI
      • 9.9.8.3 E1 Automatic Alarm Generation
      • 9.9.8.4 Receive AIS-CI and RAI-CI Detection
      • 9.9.8.5 T1 Receive-Side Digital Milliwatt Code Generation
    • 9.9.9 Error Count Registers
      • 9.9.9.1 Line Code Violation Count Register (LCVCR)
      • 9.9.9.2 Path Code Violation Count Register (PCVCR)
      • 9.9.9.3 Frames Out of Sync Count Register (FOSCR)
      • 9.9.9.4 E-Bit Counter (EBCR)
    • 9.9.10 DS0 Monitoring Function
    • 9.9.11 Transmit Per-Channel Idle Code Generation
    • 9.9.12 Receive Per-Channel Idle Code Insertion
    • 9.9.13 Per-Channel Loopback
    • 9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
    • 9.9.15 T1 Programmable In-Band Loop Code Generator
    • 9.9.16 T1 Programmable In-Band Loop Code Detection
    • 9.9.17 Framer Payload Loopbacks
  • 9.10 HDLC Controllers
    • 9.10.1 Receive HDLC Controller
      • 9.10.1.1 HDLC FIFO Control
      • 9.10.1.2 Receive Packet Bytes Available
      • 9.10.1.3 HDLC Status and Information
      • 9.10.1.4 HDLC Receive Example
    • 9.10.2 Transmit HDLC Controller
      • 9.10.2.1 FIFO Information
      • 9.10.2.2 HDLC Transmit Example
  • 9.11 Power-Supply Decoupling
  • 9.12 Line Interface Units (LIUs)
    • 9.12.1 LIU Operation
    • 9.12.2 Transmitter
      • 9.12.2.1 Transmit-Line Pulse Shapes
      • 9.12.2.2 Transmit G.703 Section 10 Synchronization Signal
      • 9.12.2.3 Transmit Power-Down
      • 9.12.2.4 Transmit Short-Circuit Detector/Limiter
      • 9.12.2.5 Transmit Open-Circuit Detector
    • 9.12.3 Receiver
      • 9.12.3.1 Receive Internal Termination
      • 9.12.3.2 Receive Level Indicator
      • 9.12.3.3 Receive G.703 Section 10 Synchronization Signal
      • 9.12.3.4 Receiver Monitor Mode
      • 9.12.3.5 Loss of Signal
      • 9.12.3.6 ANSI T1.231 for T1 and J1 Modes
      • 9.12.3.7 ITU-T G.775 for E1 Modes
      • 9.12.3.8 ETS 200 233 for E1 Modes
    • 9.12.4 Hitless Protection Switching (HPS)
    • 9.12.5 Jitter Attenuator
    • 9.12.6 LIU Loopbacks
      • 9.12.6.1 Analog Loopback
      • 9.12.6.2 Local Loopback
      • 9.12.6.3 Remote Loopback 1
      • 9.12.6.4 Remote Loopback 2
      • 9.12.6.5 Dual Loopback
  • 9.13 Bit Error-Rate Test Function (BERT)
    • 9.13.1 BERT Repetitive Pattern Set
    • 9.13.2 BERT Error Counter
• 10. DEVICE REGISTERS
  • 10.1 Register Listings
    • 10.1.1 Global Register List
      • FRAMER 1
      • FRAMER 9
    • 10.1.2 Framer Register List
    • 10.1.3 LIU and BERT Register List
  • 10.2 Register Bit Maps
    • 10.2.1 Global Register Bit Map
    • 10.2.2 Framer Register Bit Map
    • 10.2.3 LIU Register Bit Map
    • 10.2.4 BERT Register Bit Map
  • 10.3 Global Register Definitions
    • FRAMER 1
      • FRAMER 9
      • GPIORR1
  • 10.4 Framer Register Descriptions
    • 10.4.1 Receive Register Descriptions
      • Receive Idle Code Definition Registers 1 to 32
      • Receive SLC96 Data Link Registers
      • Received Sa7 Bits Register
      • Received SaX Bits Register
      • E1 Receive Digital Milliwatt Enable Registers 1 to 4
      • Receive-Signaling Change of State Enable Registers 1 to 4
      • RHPBA
      • Receive-Signaling Reinsertion Enable Registers 1 to 4
      • 0D4h, 0D5h, 0D6h, 0D7h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
    • 10.4.2 Transmit Register Descriptions
      • Software-Signaling Insertion Enable Registers 1 to 4
      • TS1 to TS16
      • Transmit Control Register 1
      • THF
  • 10.5 LIU Register Definitions
  • 10.6 BERT Register Definitions
• 11. FUNCTIONAL TIMING
  • 11.1 T1 Receiver Functional Timing Diagrams
  • 11.2 T1 Transmitter Functional Timing Diagrams
  • 11.3 E1 Receiver Functional Timing Diagrams
  • 11.4 E1 Transmitter Functional Timing Diagrams
• 12. OPERATING PARAMETERS
  • 12.1 Thermal Characteristics
  • 12.2 Line Interface Characteristics
• 13. AC TIMING CHARACTERISTICS
  • 13.1 Microprocessor Bus AC Characteristics
    • 13.1.1 SPI Bus Mode
  • 13.2 JTAG Interface Timing
  • 13.3 System Clock AC Characteristics
• 14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT
  • 14.1 TAP Controller State Machine
    • 14.1.1 Test-Logic-Reset
    • 14.1.2 Run-Test-Idle
    • 14.1.3 Select-DR-Scan
    • 14.1.4 Capture-DR
    • 14.1.5 Shift-DR
    • 14.1.6 Exit1-DR
    • 14.1.7 Pause-DR
    • 14.1.8 Exit2-DR
    • 14.1.9 Update-DR
    • 14.1.10 Select-IR-Scan
    • 14.1.11 Capture-IR
    • 14.1.12 Shift-IR
    • 14.1.13 Exit1-IR
    • 14.1.14 Pause-IR
    • 14.1.15 Exit2-IR
    • 14.1.16 Update-IR
  • 14.2 Instruction Register
    • 14.2.1 SAMPLE:PRELOAD
    • 14.2.2 BYPASS
    • 14.2.3 EXTEST
    • 14.2.4 CLAMP
    • 14.2.5 HIGHZ
    • 14.2.6 IDCODE
  • 14.3 JTAG ID Codes
  • 14.4 Test Registers
    • 14.4.1 Boundary Scan Register
    • 14.4.2 Bypass Register
    • 14.4.3 Identification Register
• 15. PIN CONFIGURATION
  • 15.1 Pin Configuration—484-Ball HSBGA
• 16. PACKAGE INFORMATION
  • 16.1 484-Ball HSBGA (56-G6038-002)
• 17. DOCUMENT REVISION HISTORY