GE Industrial Solutions CAR2512TE Front-End - Manual (Page 8)

GE
Preliminary Data Sheet
CAR2512TE Front-End
Input: 90V
AC
to 264V
AC
; Output: 12 V
DC
@ 2500W; 3.3/5V
DC
standby @ 15W
February 7, 2014 ©2013 General Electric Company. All rights reserved. Page 8
Remote sense: The two sense pins regulate the 12Vdc output
at the termination point external to the power supply. Up to
0.5V of total load cable voltage drop to the sense point is
tolerable.
Status Signals
Current monitor (Imon): A voltage level proportional to the
delivered output current is present on this pin. The signal level
is typically 15mV per amp.
Input_OK: A TTL compatible status signal representing
whether the input voltage is within the anticipated range. This
signal is pulled HI internally through a 10kΩ resistor.
DC_OK: A TTL compatible status signal representing whether
the output voltage is present. This signal needs is pulled HI
internally through a 10kΩ resistor.
Over_temp_warning#: A TTL compatible status signal
representing whether an over temperature exists This signal is
pulled HI internally through a 10kΩ resistor.
If an over temperature should occur, this signal would pull LO
approximately 10 seconds prior to shutting down the power
supply. The unit would restart if internal temperatures recover
within normal operational levels. At that time the signal reverts
back to its open collector (HI) state.
Fault#: A TTL compatible status signal representing whether
a Fault occurred. This signal is pulled HI internally through a
10kΩ resistor.
This signal activates for OTP, OVP, OCP, INPUT fault or No
output.
PS_Present#: This pin is connected to ‘output return’ within the
power supply. Its intent is to indicate to the system that a
power supply is present. This signal may need to be pulled HI
externally through a resistor.
SMBAlert# (Interrupt): A TTL compatible status signal,
representing the SMBusAlert# feature of the PMBus compatible
i
2 C protocol in the power supply. This signal is pulled HI
internally through a 10kΩ resistor.
Serial Bus Communications
The I²C interface facilitates the monitoring and control of
various operating parameters within the unit and transmits
these on demand over an industry standard I²C Serial bus.
Serial Clock (SCL): Clock pulses are host generated initiating
communications across the I²C Serial bus. Pulled up internally
to 3.3V by a 10kΩ resistor. The end user should add additional
pull up resistance as necessary to ensure that rise and fall time
timing and the maximum sink current is in compliance to the
I²C specifications.
Serial Data (SDA): This is a bi-directional data line. . Pulled up
internally to 3.3V by a 10kΩ resistor. The end user should add
additional pull up resistance as necessary to ensure that rise
and fall time timing and the maximum sink current is in
compliance to the I²C specifications.
Basic Operation
PMBus™ compliance: The power supply is fully compliant to
the Power Management Bus (PMBus™) rev1.2 requirements.
Manufacturer specific commands located between addresses
0xD0 to 0xEF provide instructions that either do not exist in the
general PMBus specification or make the communication
interface simpler and more efficient.
Master/Slave: The ‘host controller’ is always the MASTER.
Power supplies are always SLAVES. SLAVES cannot initiate
communications or toggle the Clock. SLAVES also must
respond expeditiously at the command of the MASTER as
required by the clock pulses generated by the MASTER.
Clock stretching: The ‘slave’ µController inside the power
supply may initiate clock stretching if it is busy and it desires to
delay the initiation of any further communications. During the
clock stretch the ‘slave’ may keep the clock LO until it is ready
to receive further instructions from the host controller. The
maximum clock stretch interval is 25ms.
The host controller needs to recognize this clock stretching,
and refrain from issuing the next clock signal, until the clock
line is released, or it needs to delay the next clock pulse
beyond the clock stretch interval of the power supply.
Note that clock stretching can only be performed after
completion of transmission of the 9
th ACK bit, the exception
being the START command.
Figure 1. Example waveforms showing clock stretching.
I ²C Bus Lock-Up detection: The device will abort any
transaction and drop off the bus if it detects the bus being held
low for more than 35ms.
Communications speed: Both 100kHz and 400kHz clock rates
are supported. The power supplies default to the 100kHz clock
rate. The minimum clock speed specified by SMBus is 10 kHz.
Packet Error Checking (PEC): Although the power supply will
respond to commands with or without the trailing PEC, it is
highly recommended that PEC be used in all communications.
The integrity of communications is compromised if packet
error correction is not employed. There are many functional
features, including turning OFF the main output, that should
require validation to ensure that the correct command is
executed.
PEC is a CRC-8 error-checking byte, based on the polynomial
C(x) = x
8 + x 2 + x + 1, in compliance with PMBus™
requirements. The calculation is based in all message bytes,
including the originating write address and command bytes
preceding read instructions. The PEC is appended to the
message by the device that supplied the last byte.
Clock
Stretch