Diodes ZVP4105A User Manual

Zvp4105a, P-channel enhancement mode vertical dmos fet

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P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET

ISSUE 2 – MARCH 94
FEATURES
* 50 Volt V

DS

* R

DS(on)

=10

* Low threshold

ABSOLUTE MAXIMUM RATINGS.

PARAMETER

SYMBOL

VALUE

UNIT

Drain-Source Voltage

V

DS

-50

V

Continuous Drain Current at T

amb

=25°C

I

D

-175

mA

Pulsed Drain Current

I

DM

-520

mA

Gate Source Voltage

V

GS

±

20

V

Power Dissipation at T

amb

=25°C

P

tot

625

mW

Operating and Storage Temperature Range

T

j

:T

stg

-55 to +150

°C

ELECTRICAL CHARACTERISTICS (at T

amb

= 25°C unless otherwise stated).

PARAMETER

SYMBOL MIN. MAX. UNIT CONDITIONS.

Drain-Source Breakdown

Voltage

BV

DSS

-50

V

I

D

=-0.25mA, V

GS

=0V

Gate-Source Threshold

Voltage

V

GS(th)

-0.8

-2.0

V

ID=-1mA, V

DS

= V

GS

Gate-Body Leakage

I

GSS

10

nA

V

GS

=

±

20V, V

DS

=0V

Zero Gate Voltage Drain

Current

I

DSS

-15

-60

-100

µ

A

µ

A

nA

V

DS

=-50V, V

GS

=0V

V

DS

=-50V, V

GS

=0V, T=125°C

(2)

V

DS

=-25V, V

GS

=0V

Static Drain-Source On-State

Resistance (1)

R

DS(on)

10

V

GS

=-5V,I

D

=-100mA

Forward Transconductance

(1)(2)

g

fs

50

mS

V

DS

=-25V,I

D

=-100mA

Input Capacitance (2)(4)

C

iss

40

pF

Common Source Output

Capacitance (2)(4)

C

oss

15

pF

V

DS

=-25V, V

GS

=0V, f=1MHz

Reverse Transfer

Capacitance (2)(4)

C

rss

6

pF

Turn-On Delay Time (2)(3)(4) t

d(on)

10

ns

V

DD

-30V, I

D

=-270mA

Rise Time (2)(3)(4)

t

r

10

ns

Turn-Off Delay Time (2)(3)(4) t

d(off)

18

ns

Fall Time (2)(3)(4)

t

f

25

ns

(1) Measured under pulsed conditions. Width=300

µ

s. Duty cycle

2%

(2) Sample test.

(3) Switching times measured with 50

source impedance and <5ns rise time on a pulse generator

(

4

)

E-Line

TO92 Compatible

ZVP4105A

3-435

D

G

S

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