Diodes ZLNB101 - Manual (Page 3)

Note:-
1) V
POL1
and V
POL2
switching thresholds apply over the whole operating temperature range
specified above.
2) Inputs V
POL1
and V
POL2
are designed to be wired to the power input of an LNB via high value
(10k) resistors. Input V
POL1
controls outputs Vert1 and Hor1. Input V
POL2
controls outputs Vert2
and Hor2. With either input voltage set at or below 14V, the corresponding Vert pin will be high
and Hor pin low. With either input voltage at or above 15.0V, the corresponding Vert pin will be
low and Hor pin high. Any input or output not required may be left open-circuit.
3) All outputs are designed to be compatible with TTL, CMOS, pin diode and IF Amp loads.
4) Applied via 10k resistors
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Bias Generator
ZNBG40XX
Series
ZLNB101 Series
Dual H/V Switch
Vertical
Antenna
Horizontal
Antenna Gain Stage
GaAs/HEMTFET
Gain Stage
GaAs/HEMTFET
1
4 2
IF down feed
950-1750 MHz
- Standard Band
950-2050 MHz
- Enhanced Band
+
+
Mixer
Mixer
H/V Output 2
H/V Output 1
3
Control Input
<=14V-Horizontal
>=15V-Vertical
Control
Horizontal
Vertical
PIN
Diode
MUX
DC Input
13-25V
The following block diagram shows a typical block diagram twin LNB design. The ZLNB101
provides the two polarity switches required to decode the two independent receiver feeds.
Additionally the front end bias requirements of the LNB are provided by the ZNBG4000 or
ZNBG6000 offering a very efficient and cost effective solution.
ZLNB101
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