Ap3440 – Diodes AP3440 User Manual

Page 9

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AP3440

Document number: DS36691 Rev. 2 - 2

9 of 15

www.diodes.com

March 2014

© Diodes Incorporated

AP3440

A Product Line of

Diodes Incorporated

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Application Note

(Cont.)

Resistor R1 can be calculated according to equation 4.

1

803

.

0

2

1

OUT

V

R

R

……………………….. (4)

AP3440

R1

R2

V

OUT

FB

0.803V

SS

Figure 2. Voltage Divider Circuit

Synchronize Using the RT/CLK Pin

The RT/CLK pin of AP3440 is used to synchronize the converter with an external system clock referring to Figure 3. To implement the

synchronization feature in a system, connect a square wave to the RT/CLK pin with an on-time of at least 75ns. When the clock is detected on the

RT/CLK pin, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled. If clocking edges stop, the

internal amplifier is re-enabled and the mode returns to the frequency set by the resistor. The low level of the square wave must be lower than

0.6V and the high level higher than 1.6V typically. The synchronization frequency range is from 300kHz to 2000kHz. The rising edge of the SW is

synchronized to the falling edge of RT/CLK pin. Figure 4 shows a typical synchronizing waveform, the clock frequency is 2MHz.

AP3440

R

T

RT/CLK

Clock

Source

Figure 3. Synchronizing to a System Clock

Figure 4. Synchronizing Waveform

Constant Switching Frequency and Timing Resistor

The switching frequency of the AP3440 is adjustable over a wide range from 200kHz to 2000kHz by placing a resistor with maximum value of

1000k

Ω and minimum of 85kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when connecting an external

resistor to ground to set the switching frequency. The V

RT/CLK

is typically 0.5V. To determine the timing resistance for a given switching frequency,

use the equation 5.

0793

.

1

)

(

311890

)

(

kHz

f

k

R

SW

T

……………………….(5)

9393

.

0

)

(

133870

)

(

k

R

kHz

f

T

SW

………………………..(6)

To reduce the solution size one should typically set the switching frequency as high as possible, but tradeoffs of the efficiency, maximum input

voltage and minimum controllable on time should be considered.

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