Diodes AP6503 - Manual (Page 8)

AP6503
Document number: DS35077 Rev. 5 - 2
8 of 15
www.diodes.com
January 2013
© Diodes Incorporated
AP6503
Application Information
Theory of Operation
The AP6503 is a 3A current mode control, synchronous buck regulator with built in power MOSFETs. Current mode control assures excellent
line and load regulation and a wide loop bandwidth for fast response to load transients. Figure 3 depicts the functional block diagram of AP6503.
The operation of one switching cycle can be explained as follows. At the beginning of each cycle, HS (high-side) MOSFET is off. The EA output
voltage is higher than the current sense amplifier output, and the current comparator’s output is low. The rising edge of the 340kHz oscillator
clock signal sets the RS Flip-Flop. Its output turns on HS MOSFET. The current sense amplifier is reset for every switching cycle.
When the HS MOSFET is on, inductor current starts to increase. The Current Sense Amplifier senses and amplifies the inductor current. Since
the current mode control is subject to sub-harmonic oscillations that peak at half the switching frequency, Ramp slope compensation is utilized.
This will help to stabilize the power supply. This Ramp compensation is summed to the Current Sense Amplifier output and compared to the
Error Amplifier output by the PWM Comparator. When the sum of the Current Sense Amplifier output and the Slope Compensation signal
exceeds the EA output voltage, the RS Flip-Flop is reset and HS MOSFET is turned off.
For one whole cycle, if the sum of the Current Sense Amplifier output and the Slope Compensation signal does not exceed the EA output, then
the falling edge of the oscillator clock resets the Flip-Flop. The output of the Error Amplifier increases when feedback voltage (VFB) is lower than
the reference voltage of 0.925V. This also increases the inductor current as it is proportional to the EA voltage.
If in one cycle the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. When
the HS MOSFET turns off, the synchronous LS MOSFET turns on until the next clock cycle begins. There is a “dead time” between the HS turn
off and LS turn on that prevents the switches from “shooting through” from the input supply to ground.
The voltage loop is compensated through an internal transconductance amplifier and can be adjusted through the external compensation
components.
Enable
Above the ‘EN Rising Threshold’, the internal regulator is turned on and the quiescent current can be measured above this threshold. The enable
(EN) input allows the user to control turning on or off the regulator. To enable the AP6503, EN must be pulled above the ‘EN Lockout Threshold
Voltage’ and to disable the AP6503, EN must be pulled below ‘EN Lockout Threshold Voltage - EN Lockout Hysteresis’ (2.2V-0.22V =1.98V).
External Soft Start
Soft start is traditionally implemented to prevent the excess inrush current. This in turn prevents the converter output voltage from overshooting
when it reaches regulation. The AP6503 has an internal current source with a soft start capacitor to ramp the reference voltage from 0V to
0.925V. The soft start current is 6uA. The soft start sequence is reset when there is a Thermal Shutdown, Under Voltage Lockout (UVLO) or
when the part is disabled using the EN pin.
External Soft Start can be calculated from the formula below:
DT
DV
* C
SS
I =
Where;
I
SS
= Soft Start Current
C = External Capacitor
DV=change in feedback voltage from 0V to maximum voltage
DT = Soft Start Time
Current Limit Protection
In order to reduce the total power dissipation and to protect the application, AP6503 has cycle-by-cycle current limiting implementation. The
voltage drop across the internal high-side MOSFET is sensed and compared with the internally set current limit threshold. This voltage drop is
sensed at about 30ns after the HS turns on. When the peak inductor current exceeds the set current limit threshold, current limit protection is
activated. During this time the feedback voltage (VFB) drops down. When the voltage at the FB pin reaches 0.3V, the internal oscillator shifts
the frequency from the normal operating frequency of 340Khz to a fold-back frequency of 102Khz. The current limit is reduced to 70% of nominal
current limit when the part is operating at 102Khz. This low Fold-back frequency prevents runaway current.
Under Voltage Lockout (UVLO)
Under Voltage Lockout is implemented to prevent the IC from insufficient input voltages. The AP6503 has a UVLO comparator that monitors the
input voltage and the internal bandgap reference. If the input voltage falls below 4.0V, the AP6503 will latch an under voltage fault. In this event
the output will be pulled low and power has to be re-cycled to reset the UVLO fault.