Diodes AUR9705 - Manual (Page 10)

Data Sheet
1.5MHz, 1A, STEP DOWN DC-DC CONVERTER AUR9705
Sep. 2013 Rev. 1. 2 BCD Semiconductor Manufacturing Limited
10
Application Information (Continued)
5.
Efficiency Considerations
The efficiency of switching regulator is equal to the
output power divided by the input power times 100%.
It is usually useful to analyze the individual losses to
determine what is limiting efficiency and which
change could produce the largest improvement.
Efficiency can be expressed as:
Efficiency=100%-L1-L2-…..
Where L1, L2, etc. are the individual losses as a
percentage of input power.
Although all dissipative elements in the regulator
produce losses, two major sources usually account for
most of the power losses: V
IN
quiescent current and
I 2 R losses. The V
IN
quiescent current loss dominates
the efficiency loss at very light load currents and the
I
2 R loss dominates the efficiency loss at medium to
heavy load current.
5.1 The V
IN
quiescent current loss comprises two
parts: the DC bias current as given in the electrical
characteristics and the internal MOSFET switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each cycle the gate is switched
from high to low, then to high again, and the packet
of charge, dQ moves from V
IN
to ground. The
resulting dQ/dt is the current out of V
IN
that is
typically larger than the internal DC bias current. In
continuous mode,
Where Q
P
and Q
N
are the gate charge of power
PMOSFET and NMOSFET switches. Both the DC
bias current and gate charge losses are proportional to
the V
IN
and this effect will be more serious at higher
input voltages.
5.2 I
2 R losses are calculated from internal switch
resistance, R
SW
and external inductor resistance R
L
.
In continuous mode, the average output current
flowing through the inductor is chopped between
power PMOSFET switch and NMOSFET switch.
Then, the series resistance looking into the LX pin is
a function of both PMOSFET R
DS(ON)
and NMOSFET
R
DS(ON)
resistance and the duty cycle (D):
( ) ( )
) (
D R D R
N ON DS P ON DS SW
− ×
R
1 = × +
Therefore, to obtain the I
2 R losses, simply add R
SW
to R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for
less than 2 % of total additional loss.
6. Thermal Characteristics
In most applications, the part does not dissipate much
heat due to its high efficiency. However, in some
conditions when the part is operating in high ambient
temperature with high R
DS(ON)
resistance and high
duty cycles, such as in LDO mode, the heat
dissipated may exceed the maximum junction
temperature. To avoid the part from exceeding
maximum junction temperature, the user should do
some thermal analysis. The maximum power
dissipation depends on the layout of PCB, the thermal
resistance of IC package, the rate of surrounding
airflow and the temperature difference between
junction and ambient.
) (
N P GATE
Q Q f I
+ Ч =