Diodes AP9050 - Manual (Page 2)

AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
AP9050
Document number: DS35283 Rev. 1 - 2
2 of 9
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March 2011
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Pin Descriptions
Pin # Name Description
1 Source Source of the n-channel power FET. Pass-switch’s output pin.
2 Gate Gate of the FET switch. Pass-switch’s control pin.
3, 7 V
IN
Input voltage to the internal LDO.
4 Ground LDO ground connection.
5 V
OUT
Output of the LDO.
6, 8 Drain Drain of the power FET. Pass-switch’s input pin.
Functional Block Diagram
Figure 2. Functional Block Diagram