Diodes AP2121 - Manual (Page 2)

Data Sheet
2
Dec. 2012 Rev. 2. 6 BCD Semiconductor Manufacturing Limited
HIGH SPEED, EXTREMELY LOW NOISE LDO REGULATOR AP2121
Pin Configuration
Figure 2. Pin Configuration of AP2121 (Top View)
K Package
(SOT-23-5)
NC
V
OUT
V
IN
GND
CE
N Package
(SOT-23-3)
V
IN
GND
V
OUT
Pin Description
Pin Number
Pin Name Function
SOT-23-3 SOT-23-5 CSP-4
(J4/J4A)
CSP-4
(J4C/J4B)
3 1 A2 A1 V
IN
Input voltage
1 2 B1 B2 GND Ground
3 A1 B1 CE Active high enable input pin. Logic high=enable,
logic low=shutdown
4 NC No connection
2 5 B2 A2 V
OUT
Regulated output voltage
J4/J4A Package
(CSP-4 (P 0.5)/CSP-4 (P 0.4))
3
2 1
1
2
3 4
5
A1 A2
B1 B2
Pin 1 Mark
CE V
IN
GND V
OUT
A1 A2
B1 B2
Pin 1 Mark
CE
V
IN
GND
V
OUT
J4C/J4B Package
(CSP-4 (P 0.5)/CSP-4 (P 0.4))