Impulse 7402 - Manual (Page 14)

Technical Description
Sealevel Systems ULTRA COMM+422.PCI Page 11
In the early days of PC’s Sealevel Systems decided that the ability to share IRQs
was an important feature for any add-in I/O card. Consider that in the IBM XT
the available IRQs were IRQ0 through IRQ7. Of these interrupts only IRQ2-5
and IRQ7 were actually available for use. This made the IRQ a very valuable
system resource. To make the maximum use of these system resources Sealevel
Systems devised an IRQ sharing circuit that allowed more than one port to use a
selected IRQ. This worked fine as a hardware solution but presented the software
designer with a challenge to identify the source of the interrupt. The software
designer frequently used a technique referred to as ‘round robin polling’. This
method required the interrupt service routine to ‘poll’ or interrogate each UART
as to its interrupt pending status. This method of polling was sufficient for use
with slower speed communications, but as modems increased their through put
abilities this method of servicing shared IRQs became inefficient.
Why use an ISP?
The answer to the polling inefficiency was the Interrupt Status Port (ISP). The
ISP is a read only 8-bit register that sets a corresponding bit when an interrupt is
pending. Port 1 interrupt line corresponds with Bit D0 of the status port, Port 2
with D1 etc. The use of this port means that the software designer now only has
to poll a single port to determine if an interrupt is pending.
The ISP is at Base+7 on each port (Example: Base = 280 Hex, Status Port = 287,
28F… etc.). The ULTRA COMM+422.PCI will allow any one of the available
locations to be read to obtain the value in the status register. Both status ports on
the ULTRA COMM+422.PCI are identical, so any one can be read.
Example: This indicates that Channel 2 has an interrupt pending.
Bit Position: 7 6 5 4 3 2 1 0
Value Read: 0 0 0 0 0 0 1 0