Elitegroup A960M-M3 (V1.0) - Manual (Page 47)

Chapter 3
A960M-M3 USER MANUAL
43
Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.
Version 2.14.1219. Copyright (C) 2011, American Megatrends, Inc.
Slow Access Mode
Memory Control
Memory Clock DCT0 is : (DDR-1333/667Mhz)
Memory Clock DCT1 is : None
Command Rate [Auto]
Memory Clock Mode [Auto]
Memory Timing Mode [Auto]
CAS Latency 9
RAS to CAS Delay 9
Row Precharge Time 9
RAS Active Time 24
Row Cycle Time 33
RAS to RAS Delay 4
Read CAS to Precharge Time 5
+/- : Change Opt.
lk
mn
: Select Screen
/Click: Select Item
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC/Right Click: Exit
Enter/Dbl Click : Select
fMemory Control
Scroll to this item and press <Enter> to view the following screen.
Memory Clock DCT0 is DDR-1333/667Mhz
This item shows current memory clock of DCTO.
Memory Clock DCT1 is None
This item shows current memory clock of DCT1.
RAS Active Time (24)
This item specifies the RAS# active time.
Memory Clock Mode (Auto)
This item is used to set the memory clock Mode.
RAS to CAS Delay (9)
This item specifies the RAS# to CAS# delay to Rd/Wr command to the same bank.
Memory Timing Mode (Auto)
This item is used to set the memory Timing Mode.
Row Precharge Time (9)
This item specifies Row precharge to Active or Auto-Refresh of the same bank.
CAS Latency (9)
This item determines the operation of DDR SDRAM memory CAS (column address
strobe). It is recommanded that you leave this item at the default value. The 2Tsetting
requires faster memory that specifically supports this mode.
Row Cycle Time (33)
Use this item to specify the Row Cycle Time.
Command Rate (Auto)
RAS to CAS Delay (4)
Read CAS to Precharge Time (5)
Read to Precharge Delay, range from 4 to 15.
This item specifies the active-to-active delay of different banks.
This item is used to set the Command Rate.
Main Advanced Chipset M.I.B.III Boot Security Exit