Figure 3.24 south bridge chipset configuration, 3 me subsystem configuration, Figure 3.24south bridge chipset configuration – Advantech AIMB-766 User Manual

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AIMB-766 User Manual

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Figure 3.24 South Bridge Chipset Configuration

3.11.3

ME Subsystem Configuration

ME-HECI:Enable/disable ME-H
ME-IDER:Enable/disable ME-IDER
ME-KT: Enable/Disable ME-KT

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