Single-processor configuration, Dual-processor configuration – Acer AN1600 User Manual

Page 12

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Acer AN1600 F1 Network Storage System Specifications

Independent mode (please refer to the User Guide for more information)

In this mode all memory is accessible and ECC protected

Single-processor configuration

Total

Memory

P1

1B

P1

1A

P1

2B

P1

2A

P1

3B

P1

3A

2GB

2GB

4GB

2GB

2GB

6GB

2GB

2GB

2GB

8GB

2GB

2GB

2GB

2GB

12GB

2GB

2GB

2GB

2GB

2GB

2GB

4GB

4GB

8GB

4GB

4GB

12GB

4GB

4GB

4GB

16GB

4GB

4GB

4GB

4GB

24GB

4GB

4GB

4GB

4GB

4GB

4GB

8GB

8GB

16GB

8GB

8GB

24GB

8GB

8GB

8GB

32GB

8GB

8GB

8GB

8GB

Dual-processor configuration

CPU1

CPU2

Total

Memory

P1

1B

P1

1A

P1

2B

P1

2A

P1

3B

P1

3A

P2

1B

P2

1A

P2

2B

P2

2A

P2

3B

P2

3A

4GB

2GB

2GB

8GB

2GB

2GB

2GB

2GB

12GB

2GB

2GB

2GB

2GB

2GB

2GB

16GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

18GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

24GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

2GB

8GB

4GB

4GB

16GB

4GB

4GB

4GB

4GB

24GB

4GB

4GB

4GB

4GB

4GB

4GB

32GB

4GB

4GB

4GB

4GB

4GB

4GB

4GB

4GB


Mirroring mode:

In mirroring mode, the memory contains a primary image and a copy of the primary image therefore the
effective size of memory is reduced by one half.

Channel 3 has no function in these modes.

Follow the population rules described in independent mode.

Mirroring mode needs the channel 1 & channel 2 DIMMs to be identical. DIMM slot populations within a
channel do not have to be identical but the same DIMM slot location across channel 1 and channel 2
must be the same. DIMM1A and DIMM2A should be the same type, size and manufacturer. DIMM1B
and DIMM2B memory should be the same type, size and manufacturer. DIMM1C and DIMM2C
memory should be the same type, size and manufacturer.

Same rules apply to CPU2.

Please refer to the User Guide for complete population rules for both single and dual processor
configurations.


Lockstep mode:

In Lockstep Channel Mode, each memory access is 128-bit data access that spans Channel 1 and
Channel 2. This is done to support SDDC for DRAM devices with 8-bit wide data ports. The same
address is used on both channels such that an address error on any channel is detectable.

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