Cirrus Logic CS1613A - Manual (Page 9)

CS1610A/11A
CS1612A/13A
DS976F1 9
5.3.4 Leading-edge Mode
In Leading-edge Mode, the CS1610A/11A/12A/13A regulates
boost output voltage V
BST
while maintaining the dimmer phase
angle (see Figure 9). The device executes a CCM boost
algorithm using dimmer attach current as the initial peak current
on the initial firing event of the dimmer. After gaining control of
the incoming current, the device transitions to a CRM boost
algorithm to regulate the boost output voltage. The device
periodically executes a probe event on the incoming waveform.
The information from the probe event is beneficial to
maintaining proper operation with the dimmer circuitry.
5.3.5 Trailing-edge Mode
In Trailing-edge Mode, the CS1610A/11A/12A/13A determines
its operation based on the falling edge of the input voltage
waveform (see Figure 10). To allow the dimmer to operate
properly, the CS1610A/11A/12A/13A must charge the
capacitor in the dimmer on the falling edge of the input voltage.
To accomplish this, the CS1610A/11A/12A/13A always
executes the boost algorithm on this falling edge. To ensure
maximum compatibility with dimmer components, the device
boosts during this falling edge event using a peak current that
must meet a minimum value. In Trailing-edge Mode, only CRM
boosting is used.
5.3.6 Center-cut Mode
In Center-cut Mode, the CS1610A/11A/12A/13A determines
its operation based on the leading-edge, zero-crossing and
falling edge of the input voltage waveform (see Figure 11). To
provide proper dimmer operation, the device implements the
same techniques used in the Leading-edge Mode. The boost
algorithm uses the dimmer attach current as the initial peak
current for the initial firing event of the dimmer. Additionally, the
CS1610A/11A/12A/13A provides a low impedance path
during the zero-crossing event of the input waveform and uses
trailing-edge mode techniques to charge the dimmer capacitor
on the falling edge of the input waveform.
5.4 Boost Stage
The high-voltage FET in the source-follower startup circuit is
source-switched by a variable current source on the SOURCE
pin to operate a boost circuit. Peak FET switching current is
set with an external resistor on pin IPK.
In No-dimmer Mode, the boost stage begins operating when
the start threshold is reached during each rectified half line-cy-
cle and is disabled at the nominal boost output voltage. The
peak FET switching current determines the percentage of the
rectified input voltage conduction angle over which the boost
stage will operate. The control algorithm adjusts the peak FET
switching current to maximize the operating time of the boost
stage, thus improving the input power factor.
When operating in Leading-edge Mode, the boost stage
ensures the hold current requirement of the dimmer is met
from the initiation of each half-line dimmer conduction cycle
until the peak of the rectified input voltage. The Trailing-edge
Mode boost stage ensures that the trailing-edge is exposed at
the correct time with the correct current.
Figure 9. Leading-edge Mode Phase Cut Waveform
Figure 10. Trailing-edge Mode Phase Cut Waveform
Figure 11. Center-cut Mode Phase Cut Waveform