Cirrus Logic CS3002 - Manual (Page 10)

CS3002
10 DS490F10
Equation 4 is used to determine transfer function zero
Z
1.
where
|A| = R2/R1
Substituting A into Equation 4 then zero Z
1
is:
Equation 6 is used to determine the transfer function
pole P
1
.
where
R2>>R1
This indicates that the separation of the pole and the
zero is governed by the closed loop gain. It is required
that the zero falls on the steep slope (-100dB/decade)
of the loop gain plot so that there is some gain higher
than 0dB (typically 20dB) at the hand-over frequency
(the frequency at which the slope changes
from -100dB/decade to -20dB/decade). The loop gain
plot shown in
Figure 16 illustrates the unity gain
configuration, and indicates how this is modified when
using the amplifier in a higher gain configuration with
compensation. If it is configured for higher gain, for
example, 60dB, the x-axis will move up by 60dB (line
B). Capacitor C2 adds a zero and a pole. The modified
plot indicates the effects of introducing the pole and
zero due to capacitor C2. The pole can be located at any
frequency higher than the hand-over frequency, the
zero has to be at a frequency lower than the hand-over
frequency so as to provide adequate gain margin. The
separation between the pole and the zero is governed
by the closed loop gain. The zero (Z
1
) occurs at the
intersection of the -100dB/decade and -80dB/decade
slopes. The point X in the figure should be at closed
loop gain plus 20dB gain margin. The value for
capacitor C2 is determined by Equation 7. Setting the
pole of the filter to P
1
= 1MHz works very well and is
independent of gain. As the closed loop gain is
changed, the zero location is also modified if R1
remains fixed. Capacitor C2 can be increased in value
to limit the amplifier’s rising noise above 2kHz.
Z
1
1
2  A R1    C2  
-------------------------------------------------- = [Eq. 4]
Z
1
1
2  R2 C2  
----------------------------------- = [Eq. 5]
P
1
1
2  R1 R2    C2  
-----------------------------------------------------
1
2  R1 C2  
-----------------------------------  =
[Eq. 6]
C2
1
2  R1 P
1
 
---------------------------------- = [Eq. 7]
-100 dB/dec
|T| (Log gain)
-80 dB/dec
z
1
p
1
Margin
-20 dB/dec
50kHz 1MHz 5MHz
Desired Closed
Loop Gain
X
FREQUENCY
B
Figure 16. Loop Gain Plot: Unity Gain and with Pole-zero Compensation