Cirrus Logic CS42528 - Manual (Page 79)

DS586F2 79
CS42528
10.1.2 Jitter Attenuation
Figures 28 and 29 show the jitter-attenuation characteristics for the 32-192 kHz sample rate range when
used with the external PLL component values and locking modes as specified in Table 21 .
The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates less than
32 kHz or for locking to the SAI_LRCK input. These specifications state a maximum of 2 dB jitter gain or
peaking.
Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2
Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3