Cirrus Logic CDB4271 - Manual (Page 10)

CDB4271
10
JUMPER /
SWITCH PURPOSE POSITION FUNCTION SELECTED
M/S[1:0]
(S1)
Subclock Master/Slave Select *00
01
10
11
CS4271 is Master
CS8416 is Master
CS8406 is Master
PCM Header, J26, is Master
MCLK[1:0]
(S1)
Master Clock Source Select *00
01
10
11
CS8416 Provides MCLK
CS4271 Provides MCLK
PCM Header, J26, Provides MCLK
PCM Header, J26, Provides MCLK
Header/8416
(S1)
CS4271 SDIN Source Select *0
1
CS8416 Provides SDIIN
PCM Header, J26, Provides SDIN
Coaxial/
Optical
(S1)
Optical or Coaxial S/PDIF
Input Select
*0
1
Optical Input
Coaxial Input
I2S/LJ
(S1)
Digital Interface Format Select *0
1
Left Justified, 24-bit
I
2
S, 24-Bit
128/256
(S1)
Master Clock Speed Select *0
1
256*Fs
128*Fs
M[1:0]
(S1)
CS4271 Speed Mode Select 00
*01
10
11
Single-Speed Mode, with De-emphasis
Single-Speed Mode, w/out De-emphasis
Double-Speed Mode
Quad-Speed Mode
J11, J19 Selects LED or Mute Circuit for
AOUTA, AOUTB
1
*2
Mute Circuit Affects Analog Output
Mute Circuit Disconnected (LED displays
xMUTEC status)
J10 Selects source of voltage for
the VA supply
*+5V
ADJ
Voltage source is J1, +5.0 V binding post
Voltage source is J5, VA binding post
J9 Selects source of voltage for
the VD supply
*+5V
+3.3V
ADJ
Voltage source is J1, +5V binding post
Voltage source is +3.3 V regulator
Voltage source is J3, VD binding post
J8 Selects source of voltage for
the VL supplies
*+5V
+3.3V
ADJ
Voltage source is J1, +5V binding post
Voltage source is +3.3 V regulator
Voltage source is J2, VL binding post
J13, J14,
J15, J20,
J21, J22
Selects DAC Output Filter *1
2
Selects standard 2-pole filter
Inserts instrumentation-amp and resistor
divider.
*Default factory settings
Table 2. Jumper/Switch Settings