Cirrus Logic CS4272 - Manual (Page 23)

CS4272
DS593F1 23
4. TYPICAL CONNECTION DIAGRAM
) LJ (I2S/ CS / AD0
SDA / CDIN (M1)
SCL / CCLK (M0)
AINA+
AINA-
AINB+
AINB-
RST
Power Down
and Mode
Settings
(Control Port)
XTI
XTO
AOUTA-
AOUTA+
AMUTEC
AOUTB-
AOUTB+
BMUTEC
Analog Conditioning
&
Mute
LRCK
SCLK
MCLK
Timing Logic
&
Clock
SDIN
) S (M/ SDOUT Audio Data
Processor
DGND
FILT+
AGND
VCOM
VD VA
+5 V
+5 V to 3.3 V
CS4272
VL
40 pF
40 pF
* *
¤ See "Master/Slave Mode Selection".
¤
+5 V to 2.5 V
47 k
Ω
5.1 Ω
**
** Optional. See "Crystal
Applications (XTI/XTO)".
Analog Input
Buffer
47 µF 0.1 µF
1 µF 0.1 µF
1 µF 0.1 µF
1 µF 0.1 µF
1 µF 0.1 µF
* Only one must be used. See
"Grounding and Power Supply
Decoupling."
∗ Not to exceed 1 µF.
∗
Figure 8. CS4272 Typical Connection Diagram