Cirrus Logic CDB42L55 - Manual (Page 24)

24
DS77
3DB1
CDB42L55
7 CDB42L55 BLOCK DIAGRAM
Figure 36. Block Diagram
USB
Serial
PC Control Board Power
External 5.0 V
Supply
LDO’s
Buck
(not included)
1.8 V
2.5 V
3.3 V
1.8 V
CS42L55 FPGA
24 MHz
Oscillator
Clock/Data Routing
Clock dividers and PLL used
to derive all applicable Fs
from 24 MHz oscillator
PLL
I²C for all
applicable
devices
LDO
VL, VCP, VLDO, VA
MUX
3.3 V (VL only)
Circuit Break for
External System
Interface
PCM
Clocks/Data
I²C Clocks/
Data
I/O Stake Headers for Audio
Precision’s Programmable Serial
Interface Adapter (PSIA)
I/O SMA Connectors
for External System
Interface
Tri-state
Buffers
SRC (Rx) SRC (Tx)
S/PDIF Rx
S/PDIF Tx
Stereo
Input 1
Stereo
Input 2
Stereo HP
Output
Stereo Line
Output
HP
Jack
x3
AAA Alkaline
CODEC Power