Document Outline

• 192-kHz Stereo DAC with Integrated PLL
• 1 Pin Description
• 2 Characteristics and Specifications
  • 2.1 Recommended Operating Conditions
    • Table 1. Recommended Operating Conditions
  • 2.2 Absolute Maximum Ratings
    • Table 2. Absolute Maximum Ratings
  • 2.3 DAC Analog Characteristics - Commercial (-CZZ)
    • Table 3. DAC Analog Characteristics - Commercial (-CZZ)
  • 2.4 DAC Analog Characteristics - Automotive (-DZZ)
    • Table 4. DAC Analog Characteristics - Automotive (-DZZ)
    • Figure 1. Equivalent Output Load
    • Figure 2. Maximum Loading
    • Figure 3. THD+N vs Output Amplitude for VA = 5.0 V
    • Figure 4. THD+N vs Output Amplitude for VA = 3.3 V
    • Figure 5. THD+N vs Output Amplitude for VA = 3.14 V
  • 2.5 Combined Interpolation and On-Chip Analog Filter Response
    • Table 5. Combined Interpolation and On-Chip Analog Filter Response
  • 2.6 Switching Specifications - Serial Audio Interface
    • Table 6. Switching Specifications - Serial Audio Interface
    • Figure 6. Serial Port Timing, Non-TDM Mode
    • Figure 7. Serial Port Timing, TDM Mode
  • 2.7 Switching Characteristics - Control Port - I²C Format
    • Table 7. Switching Characteristics - Control Port - I²C Format
    • Figure 8. Control Port Timing - I²C Format
  • 2.8 Switching Characteristics - Control Port - SPI Format
    • Table 8. Switching Characteristics - Control Port - SPI Format
    • Figure 9. Control Port Timing - SPI Mode
  • 2.9 Digital Characteristics
    • Table 9. Digital Characteristics
  • 2.10 Power and Thermal Characteristics
    • Table 10. Power and Thermal Characteristics
• 3 Typical Connection Diagram
  • Figure 10. Typical Connection Diagram
• 4 Applications
  • 4.1 Sample Rate Range and Oversampling Mode Detect
    • 4.1.1 Sample Rate Auto-Detect
      • Table 11. CS4350 Auto-Detect
  • 4.2 System Clocking
    • 4.2.1 Recovered Master Clock (RMCK)
  • 4.3 Digital Interface Format
    • Figure 11. Left-Justified up to 24-Bit Data
    • Figure 12. I²S, up to 24-Bit Data
    • Figure 13. Right-Justified Data
    • 4.3.1 Time-Division Multiplex (TDM) Mode
      • Figure 14. TDM Mode Connection Diagram
      • Figure 15. TDM Mode Timing
  • 4.4 De-Emphasis
    • Figure 16. De-Emphasis Curve
  • 4.5 Mute Control
  • 4.6 Recommended Power-Up Sequence
    • 4.6.1 Stand-Alone Mode
    • 4.6.2 Control Port Mode
  • 4.7 Popguard Transient Control
    • 4.7.1 Power-Up
    • 4.7.2 Power-Down
    • 4.7.3 Discharge Time
  • 4.8 Analog Output and Filtering
    • Figure 17. Differential to Single-Ended Output Filter
    • Figure 18. Passive Single-Ended Output Filter
  • 4.9 Grounding and Power Supply Arrangements
    • 4.9.1 Capacitor Placement
• 5 Stand-Alone Operation
  • 5.1 Serial Port Format Selection
    • Table 12. Digital Interface Format - Stand-Alone Mode
  • 5.2 De-Emphasis Control
  • 5.3 Popguard Transient Control
• 6 Control Port Operation
  • 6.1 MAP Auto Increment
  • 6.2 I²C Mode
    • 6.2.1 I²C Write
    • 6.2.2 I²C Read
      • Figure 19. Control Port Timing, I²C Mode
  • 6.3 SPI Mode
    • 6.3.1 SPI Write
    • 6.3.2 SPI Read
      • Figure 20. Control Port Timing, SPI Mode
  • 6.4 Memory Address Pointer (MAP)
    • 6.4.1 INCR (Auto Map Increment Enable)
    • 6.4.2 MAP (Memory Address Pointer)
• 7 Register Quick Reference
• 8 Register Description
  • 8.1 Device and Revision ID - Register 01h
  • 8.2 Mode Control - Register 02h
    • 8.2.1 Digital Interface Format (DIF[2:0]) Bits 6-4
      • Table 13. Digital Interface Formats
    • 8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2
      • Figure 21. De-Emphasis Curve
    • 8.2.3 Functional Mode (FM[1:0]) Bits 1-0
  • 8.3 Volume Mixing and Inversion Control - Register 03h
    • 8.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7
    • 8.3.2 Invert Signal Polarity (INVERT_A) Bit 6
    • 8.3.3 Invert Signal Polarity (INVERT_B) Bit 5
    • 8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0
      • Figure 22. ATAPI Block Diagram
      • Table 14. ATAPI Decode
  • 8.4 Mute Control - Register 04h
    • 8.4.1 Auto-Mute (AMUTE) Bit 7
    • 8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5
    • 8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3
  • 8.5 Channel A & B Volume Control - Register 05h & 06h
    • Table 15. Example Digital Volume Settings
  • 8.6 Ramp and Filter Control - Register 07h
    • 8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6
    • 8.6.2 Soft Volume Ramp-Up after Error (RMP_UP) Bit 5
    • 8.6.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4
    • 8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2
  • 8.7 Misc. Control - Register 08h
    • 8.7.1 Power Down (PDN) Bit 7
    • 8.7.2 Freeze Controls (FREEZE) Bit 5
    • 8.7.3 Popguard Enable (POPG_EN) Bit 4
    • 8.7.4 RMCK control (RMCK_CTRL[1:0]) Bits 3:2
    • 8.7.5 RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1
• 9 Filter Plots
  • Figure 23. Stopband Rejection (fast), all Modes
  • Figure 24. Stopband Rejection (slow), all Modes
  • Figure 25. Single-Speed (fast) Passband Detail
  • Figure 26. Single-Speed (slow) Passband Detail
  • Figure 27. Double-Speed (fast) Passband Detail
  • Figure 28. Double-Speed (slow) Passband Detail
  • Figure 29. Quad-Speed (fast) Passband Detail
  • Figure 30. Quad-Speed (slow) Passband Detail
• 10 Parameter Definitions
• 11 Package Dimensions
• 12 Thermal Characteristics
  • Table 16. Thermal Characteristics
• 13 Ordering Information
• 14 Revision History