Cirrus Logic CS4353 - Manual (Page 12)

12 DS803F3
CS4353
3. TYPICAL CONNECTION DIAGRAM
VL +0.9 V to +3.3 V
RESET
LRCK
MCLK
SCLK
AOUT_REF
SDIN
VFILT-
AOUTA
V
A
562 
2.2 nF
R
ext
R ext
Line Level Out
Left & Right
I²S/LJ
DEM
1_2VRMS
VFILT+
Digital Audio
Processor
Hardware
Control
Values shown are for
Fc = 130 kHz.
Capacitors must be
C0G or equivalent.
562 
2.2 nF
AOUTB
VBIAS
FLYN-
FLYN+
0.1 µF
0.1 µF
2.2 µF
FLYP-
FLYP+
2.2 µF
0.1 µF
0.1 µF
+3.3 V
0.1 µF
VC
P
Note 1:
C
P
G
N
D
D
G
N
D
A
G
ND
22 µF
2.2 µF
2.2 µF
2.2 µF
Note 1
3
1
2
23
24
22
19
21
20
10 4 16
18
17 6
12
11
9
13
14
15
5
7
8
+
+
+
Note 2
Note 2:Connect RESET
to VL if internal
power-on reset is
used.
+
CS4353
Figure 3. Typical Connection Diagram