Cirrus Logic CS4364 - Manual (Page 35)

DS619F1 35
CS4364
6.3.2 Functional Mode (FM)
Default = 11
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates)
Function:
Selects the required range of input sample rates or Auto Speed Mode.
6.4 DSD Control (Address 04h)
6.4.1 DSD Mode Digital Interface Format (DSD_DIF)
Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate)
Function:
The relationship between the oversampling ratio of the DSD audio data and the required Master clock to
DSD data rate is defined by the Digital Interface Format pins.
The DSD/PCM bit determines whether PCM or DSD Mode is selected.
DIF3 DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE
0 0 0 0 Left Justified, up to 24-bit data 0 8
0 0 0 1 I
2
S, up to 24-bit data 1 9
0 0 1 0 Right Justified, 16-bit data 2 10
0 0 1 1 Right Justified, 24-bit data 3 11
0 1 0 0 Right Justified, 20-bit data 4 12
0 1 0 1 Right Justified, 18-bit data 5 13
1 0 0 0 One-line Mode 1, 24-bit Data 8 14
1 0 0 1 One-line Mode 2, 20-bit Data 9 15
X X X X All other combinations are Reserved
Table 7. Digital Interface Formats - PCM Mode
7 6 5 4 3 2 1 0
DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD STATIC_DSD INVALID_DSD DSD_PM_MD DSD_PM_EN
0 0 0 0 1 1 0 0
DIF2 DIF1 DIFO DESCRIPTION
0 0 0 64x oversampled DSD data with a 4x MCLK to DSD data rate
0 0 1 64x oversampled DSD data with a 6x MCLK to DSD data rate
0 1 0 64x oversampled DSD data with a 8x MCLK to DSD data rate
0 1 1 64x oversampled DSD data with a 12x MCLK to DSD data rate
1 0 0 128x oversampled DSD data with a 2x MCLK to DSD data rate.
1 0 1 128x oversampled DSD data with a 3x MCLK to DSD data rate.
1 1 0 128x oversampled DSD data with a 4x MCLK to DSD data rate.
1 1 1 128x oversampled DSD data with a 6x MCLK to DSD data rate.
Table 8. Digital Interface Formats - DSD Mode