4 fsin clock domain modules, 1 digital audio input port, Table 2. dai serial audio port channel allocations – Cirrus Logic CS44800 User Manual

Page 27

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DS632F1

CS44800

4.4

FsIn Clock Domain Modules

4.4.1

Digital Audio Input Port

The CS44800 interfaces to an external Digital Audio Processor via the Digital Audio Input serial port, the
DAI serial port. The DAI port has

stereo data inputs with support for I²S, left-justified and right-justified

formats. The DAI port operates in slave operation only, where DAI_LRCK, DAI_SCLK and DAI_MCLK are
always inputs. The signal DAI_LRCK must be equal to the sample rate, Fs and must be synchronously
derived from the supplied master clock, DAI_MCLK. The serial bit clock, DAI_SCLK, is used to sample
the data bits and must be synchronously derived from the master clock.

DAI_SDIN1, DAI_SDIN2, DAI_SDIN3, and DAI_SDIN4 are the serial data input pins supplying the asso-
ciated internal PWM channel modulators. The serial data interface format selection (left-justified, right-jus-
tified, I²S, one line mode, or TDM) for the DAI serial port data input pins is configured using the appropriate
bits in the register

“Misc. Configuration (address 04h)” on page 52

. The serial audio data is presented in

2's complement binary form with the MSB first in all formats.

When operated in One Line Data Mode, 6 channels of PWM data are input on DAI_SDIN1 and two addi-
tional PWM channels on DAI_SDIN4. In TDM mode, all

channels are multiplexed onto the DAI_SDIN1

data line.

Table 2

outlines the serial port channel allocations.

The DAI digital audio serial ports support 6 formats with varying bit depths from 16 to 24 as shown in

Fig-

ure 17

Figure 18

Figure 19

Figure 20

Figure 21

and

Figure 22

. These formats are selected using the

configuration bits in the

“Misc. Configuration (address 04h)” on page 52

Serial Data Inputs

Data mode

Channel Assignments

DAI_SDIN1

Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM

PWMOUTA1(left channel)/PWMOUTB1(right channel)
PWMOUTA1/A2/A3/B1/B2/B3
PWMOUTA1/A2/A3/A4/B1/B2/B3/B4

DAI_SDIN2

Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM

PWMOUTA2(left channel)/PWMOUTB2(right channel)
not used
not used

DAI_SDIN3

Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM

PWMOUTA3(left channel)/PWMOUTB3(right channel)
not used
not used

DAI_SDIN4

Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM

PWMOUTA4(left channel)/PWMOUTB4(right channel)
PWMOUTA4/B4
not used

Table 2. DAI Serial Audio Port Channel Allocations

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