Cirrus Logic CRD44600-PH-FB - Manual (Page 4)

CRD44600-PH-FB
4 MAR '05 DS633RD1
1. SYSTEM OVERVIEW
The CRD44600-PH-FB reference design is an excellent means for evaluating the CS44600 six-
channel Class-D PWM modulator. It incorporates a digital Class-D PWM modulator, two full-
bridge power stages, and power supply rejection (PSR) circuitry, all on a two-layer board.
The CRD44600-PH-FB schematic set is shown in Figures 9 through 13 and the board layout is
shown in Figures 15 through 17.
1.1 CS44600 PWM Modulator
A complete description of the CS44600 is included in the CS44600 product data sheet.
The CS44600 converts linear PCM data to pulse width modulated (PWM) output. It uses a
Sample Rate Converter (SRC) to eliminate serial audio interface jitter effects and maintains
a constant PWM switch rate of 384 kHz, resulting in high-quality sound output.
PCM data and clocks are input from either the CS8416 (S/PDIF Receiver), CS5341 (Stereo
ADC), or J19 (PCM Input Header).
1.2 CS4461 PSR Feedback ADC
A complete description of the CS4461 is included in the CS4461 product data sheet.
The CS4461 is connected to the CS44600 to provide power supply rejection (PSR) for the
VP supply voltage connected to J17. Resistors R41 and R42 are set for VP = +50 V. See the
CS4461 data sheet for equations to determine the resistor values.
1.3 TDA8939 Power Stage
A complete description of the Philips TDA8939 is included in the TDA8939 product data
sheet.
The TDA8939 is a high-voltage PWM amplifier power stage. It integrates two half-bridge driv-
ers and fault protection. For the CRD44600-PH-FB, each of the two TDA8939’s are config-
ured as full-bridges. Care should be taken to not connect the full bridge black speaker
connectors to ground as these outputs are driven.
1.4 CS8416 Digital Audio Receiver
The operation of the CS8416 receiver and a discussion of the digital audio interface are de-
scribed in the CS8416 data sheet.
The CS8416 converts the input S/PDIF data stream into PCM data for the CS44600. The
CS8416 operates in master mode with RMCK = 256*Fs. The digital Interface format is set to
Left Justified (24-bit).
D20 (RERR) indicates a receiver error, such as loss of lock.
S/PDIF input is through OPT1 or J33.
1.5 CS5341 Analog to Digital Converter
The operation of the CS5341 ADC is described in the CS5341 data sheet.