Cirrus Logic AN298 - Manual (Page 29)

AN298RC14 29
8 Watchdog Timer
8 Watchdog Timer
The CS485xx has an integrated hardware watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer
must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS485xx
will reset itself in the event of a temporary system failure. In standalone mode (no host MCU), the DSP will reboot from
external FLASH. In slave mode (host MCU present), all GPIOs will be pulled high to signal the host that the watchdog has
expired and the DSP should be rebooted and reconfigured. The watchdog timer is disabled upon reset. There are three
important registers that the host uses for configuring the watchdog timer. They are KICKSTART, WDG_RELOAD, and
WDG_COUNT.
Note: The enabling of the watchdog timer happens post-kick-start.
8.1 Watchdog Timer Messaging
The KICKSTART message is shown below, to enable the watchdog set bit 8 (a = 1). To enable no watchdog re-kicking,
set bit 9 as well (a = 3). No watching re-kicking is only used as a test hook to verify that the reset occurs when the timer
expires.
The WDG_COUNT message is shown below and reflects the watchdog state at last timer ISR. The default is abcdefgh =
FFFFFFFF.
The WDG_RELOAD message is used to set the watchdog reload time and is shown in the table below. The default is
abcdefgh = 00BB800, which is a 1 second reload time at 12.288 MHz.
The equation to calculate the watchdog reload time is shown below:
Watchdog reload time = MCLK / WDG_RELOAD
Mnemonic Value
KICKSTART 0x81000000
0x00000a00
Mnemonic Value
WDG_COUNT 0x81000018
0xabcdefgh
Mnemonic Value
WDG_RELOAD 0x81000019
0xabcdefgh