Cirrus Logic CS5344 - Manual (Page 11)

DS687F4 11
CS5343/4
Draft
2/1/11
3. TYPICAL CONNECTION DIAGRAM
Figure 3. Typical Connection Diagram
AINL
AINR
6
8
1
SDOUT
9 GND
7 VQ
VA
10
5 FILT+
2
SCLK
3
LRCK
4
MCLK
Audio
Processor/
System
Clocks
VA or
GND
VA
3.3 V to 5 V
CS5343/4
10
k

1
10
k

2
Analog Input
Conditioning
10
k

2
1 µF 0.1 µF
1 µF 0.1 µF
1 µF 0.1 µF
See Figure 6 on
page 14
1
Pull-up to VA for Master Mode
Pull-down to GND for Slave Mode
2
Optional pull-up resistor for config-
uring clocks in Master Mode as
described in the
“Master Mode Speed
Selection” section on page 13