Cirrus Logic CS5361 - Manual (Page 15)

CS5361
DS467F2 15
FILT+
AINL+
AINL-
V D
0.01
µF
A/D CONVERTER
SCLK
CS5361
M/S
MCLK
AINR+
AINR-
VQ
**47
µF
+
RST
VA V L
+5V
1
µF
+5Vto 2.5 V
5.1
Ω
1
µF
+
+ +
SDOUT
GND
I 2 S/LJ
LRCK
GND
Power Down
and Mode
Settings
Audio Data
Processor
Timing Logic
and Clock
0.01
µF
0.01
µF
0.01
µF
HPF
M0
M1
REFGND
MDIV
+5 V to 3.3 V
1
µF
0.01
µF
1
µF
+
Analog
Input
Buffer
(Figure 24)
Analog
Input
Buffer
(Figure 24)
OVFL
10 k
VL
*
0.01
µF
* Resistor may only
be used if VD is
derived from VA. If
used, do not drive any
other logic from VD.
3.0 TYPICAL CONNECTION DIAGRAM
Figure 22. Typical Connection Diagram