Document Outline

• 1. Pin Descriptions - CS5346
• 2. Pin Compatibility - cs5345/cs5346 Differences
• 3. Characteristics and Specifications
  • Recommended Operating Conditions
  • Absolute Maximum Ratings
  • Analog Characteristics
  • Analog Characteristics Cont.
  • Digital Filter Characteristics
  • DC Electrical Characteristics
  • Digital Interface Characteristics
  • Switching Characteristics - Serial Audio Port
    • Figure 1. Master Mode Serial Audio Port Timing
    • Figure 2. Slave Mode Serial Audio Port Timing
    • Figure 3. Format 0, 24-Bit Data Left-Justified
    • Figure 4. Format 1, 24-Bit Data I·S
  • Switching Characteristics - Control Port - I·C Format
    • Figure 5. Control Port Timing - I·C Format
  • Switching Characteristics - Control Port - SPI Format
    • Figure 6. Control Port Timing - SPI Format
• 4. Typical Connection Diagram
  • Figure 7. Typical Connection Diagram
• 5. Applications
  • 5.1 Recommended Power-Up Sequence
  • 5.2 System Clocking
    • Table 1. Speed Modes
    • 5.2.1 Master Clock
      • Table 2. Common Clock Frequencies
    • 5.2.2 Master Mode
      • Figure 8. Master Mode Clocking
    • 5.2.3 Slave Mode
      • Table 3. Slave Mode Serial Bit Clock Ratios
  • 5.3 High-Pass Filter and DC Offset Calibration
  • 5.4 Analog Input Multiplexer, PGA, and Mic Gain
    • Figure 9. Analog Input Architecture
  • 5.5 Input Connections
    • 5.5.1 Analog Input Configuration for 1 VRMS Input Levels
      • Figure 10. CS5346 PGA
      • Figure 11. 1 VRMS Input Circuit
      • Figure 12. 1 VRMS Input Circuit with RF Filtering
    • 5.5.2 Analog Input Configuration for 2 VRMS Input Levels
      • Figure 13. 2 VRMS Input Circuit
  • 5.6 PGA Auxiliary Analog Output
  • 5.7 Control Port Description and Timing
    • 5.7.1 SPI Mode
      • Figure 14. Control Port Timing in SPI Mode
    • 5.7.2 I·C Mode
      • Figure 15. Control Port Timing, I·C Write
      • Figure 16. Control Port Timing, I·C Read
  • 5.8 Interrupts and Overflow
  • 5.9 Reset
  • 5.10 Synchronization of Multiple Devices
  • 5.11 Grounding and Power Supply Decoupling
• 6. Register Quick Reference
• 7. Register Description
  • 7.1 Chip ID - Register 01h
    • Table 4. Device Revision
  • 7.2 Power Control - Address 02h
    • 7.2.1 Freeze (Bit 7)
      • Table 5. Freeze-able Bits
    • 7.2.2 Power-Down MIC (Bit 3)
    • 7.2.3 Power-Down ADC (Bit 2)
    • 7.2.4 Power-Down Device (Bit 0)
  • 7.3 ADC Control - Address 04h
    • 7.3.1 Functional Mode (Bits 7:6)
      • Table 6. Functional Mode Selection
    • 7.3.2 Digital Interface Format (Bit 4)
      • Table 7. Digital Interface Formats
    • 7.3.3 Mute (Bit 2)
    • 7.3.4 High-Pass Filter Freeze (Bit 1)
    • 7.3.5 Master / Slave Mode (Bit 0)
  • 7.4 MCLK Frequency - Address 05h
    • 7.4.1 Master Clock Dividers (Bits 6:4)
      • Table 8. MCLK Frequency
  • 7.5 PGAOut Control - Address 06h
    • 7.5.1 PGAOut Source Select (Bit 6)
      • Table 9. PGAOut Source Selection
  • 7.6 Channel B PGA Control - Address 07h
    • 7.6.1 Channel B PGA Gain (Bits 5:0)
  • 7.7 Channel A PGA Control - Address 08h
    • 7.7.1 Channel A PGA Gain (Bits 5:0)
      • Table 10. Example Gain and Attenuation Settings
  • 7.8 ADC Input Control - Address 09h
    • 7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
      • Table 11. PGA Soft Cross or Zero Cross Mode Selection
    • 7.8.2 Analog Input Selection (Bits 2:0)
      • Table 12. Analog Input Multiplexer Selection
  • 7.9 Active Level Control - Address 0Ch
    • 7.9.1 Active High/ Low (Bit 0)
  • 7.10 Status - Address 0Dh
    • 7.10.1 Clock Error (Bit 3)
    • 7.10.2 Overflow (Bit 1)
    • 7.10.3 Underflow (Bit 0)
  • 7.11 Status Mask - Address 0Eh
  • 7.12 Status Mode MSB - Address 0Fh
  • 7.13 Status Mode LSB - Address 10h
• 8. Parameter Definitions
• 9. Filter Plots
  • Figure 17. Single-Speed Stopband Rejection
  • Figure 18. Single-Speed Stopband Rejection
  • Figure 19. Single-Speed Transition Band (Detail)
  • Figure 20. Single-Speed Passband Ripple
  • Figure 21. Double-Speed Stopband Rejection
  • Figure 22. Double-Speed Stopband Rejection
  • Figure 23. Double-Speed Transition Band (Detail)
  • Figure 24. Double-Speed Passband Ripple
  • Figure 25. Quad-Speed Stopband Rejection
  • Figure 26. Quad-Speed Stopband Rejection
  • Figure 27. Quad-Speed Transition Band (Detail)
  • Figure 28. Quad-Speed Passband Ripple
• 10. Package Dimensions
• 11. Thermal Characteristics and Specifications
• 12. Ordering Information
• 13. Revision History