Cirrus Logic CS5372A - Manual (Page 11)

CS5371A CS5372A
DS748F3 11
DIGITAL CHARACTERISTICS (CONT.)
MCLK
MSYNC
t
MDATA
TDATA
0
(2.048 MHz)
(512 kHz)
(256 kHz)
SYNC
MFLAG
Figure 6. System Timing Diagram
MCLK
MSYNC t 0
(2.048 MHz)
t
mss
t
mclk
t
msync
t
msh
MDATA
(512 kHz)
MFLAG
t
mdata
Figure 7. MCLK / MSYNC Timing Detail