Spi™ interface timing (external master), Cs5374 – Cirrus Logic CS5374 User Manual
Page 12
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CS5374
CS5374
12
SPI™ INTERFACE TIMING (EXTERNAL MASTER)
Parameter
Symbol Min Typ
Max
Unit
SDI Write Timing
CS Enable to Valid Latch Clock
t
1
60
-
-
ns
Data Set-up Time Prior to SCK Rising
t
2
60
-
-
ns
Data Hold Time After SCK Rising
t
3
60
-
-
ns
SCK High Time
t
4
120
-
-
ns
SCK Low Time
t
5
120
-
-
ns
SCK Falling Prior to CS Disable
t
6
60
-
-
ns
SDO Read Timing
SCK Falling to New Data Bit
t
7
-
-
90
ns
SCK High Time
t
8
120
-
-
ns
SCK Low Time
t
9
120
-
-
ns
SCK Falling Hold Time Prior to CS Disable
t
10
60
-
-
ns
MSB
MSB - 1
LSB
t
6
t
5
t
4
t
3
t
2
t
1
CS
SDI
SCK
Figure 8. SDI Write Timing in SPI Slave Mode
MSB
MSB - 1
LSB
t
9
t
8
t
7
CS
SDO
SCK
t
10
Figure 9. SDO Read Timing in SPI Slave Mode
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