Cirrus Logic AN234 - Manual (Page 4)

AN234
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4.2 AK5394A
The AK5394A will automatically initiate a calibration sequence following a reset. The CAL pin (pin 9) is an
output that indicates when a calibration sequence is in progress. This calibration technique is very similar
to that described above for the CS5381.
The AK5394A also has a ZCAL pin (pin 6) which allows the calibration input to be obtained from either
the analog input pins or the VCOM pins. The high pass filter can be controlled via the HPFE pin (pin 19).
In the AK5394A, the high pass filter is either continuously running or completely removed from the signal
path.
5. Master/Slave Selection and Digital Interface Format
The CS5381 and AK5394A are pin compatible in terms of selecting Master/Slave operation and digitial
interface format. The pins match up as noted in Table 2.
6. Speed Mode Selection
The AK5394A supports three speed modes, “normal”, “double”, and “quad” as determined by the DFS0
and DFS1 pins (pins 18 and 20 respectively). These pins are compatible with the M0 and M1 pins (pins
13 and 14) of the CS5381, as shown in Table 2.
7. System Clocking
The CS5381 is fully compatible with the clocking requirements of the AK5394A. However, there is a slight
difference when operating in Master mode. When operating in “normal” mode, the AK5394A will generate
an SCLK that is 128
×
F
s
. The CS5381 generates an SCLK that is 64
×
F
s
.
The CS5381 offers an integrated MCLK divider, which can be controlled via the MDIV pin (pin 10). This
pin allows multiple external MCLK/LRCK ratios to be supported. In order to maintain complete compati-
bility between the AK5394A and the CS5381, connect the MDIV pin (pin 10) of the CS5381 to GND.
8. Input Buffer Topology
The analog input buffers shown in Figures 9 and 10 of the AK5394A datasheet (dated January, 2002) will
also work for the CS5381. In this case, the “Bias” reference (in Figure 9) should be sourced from the VQ
pin of the CS5381. However, these input buffers require a large input voltage level at the input to the buffer
and attenuate the signal prior to the converter. This much signal swing is not always possible in a real
system, and not necessary to achieve the full performance of the CS5381.
The following sections contain a description of a single-ended to differential input buffer (comparable to
Figure 9 of the AK5394A datasheet) and a fully differential input buffer (comparable to Figure 10 of the
AK5394A datasheet). These two buffer topologies are unity gain, and therefore do not rely on a large input
voltage at the buffer input.
8.1 Single-Ended to Differential Input Buffer
Figure 3 shows a single-ended to differential analog input buffer. This buffer provides the proper biasing,
isolation from the switched capacitor currents, low output impedance, and anti-alias filtering. The second
op-amp stage is set up in an inverting configuration to produce the negative node of the differential input.
In the input buffer shown below, the second stage has unity gain, and the single-ended input level will
effectively be doubled when presented differentially to the converter. For example, a 2.8 Vpp single-end-
ed input will provide a full-scale 5.6 Vpp differential input to the CS5381.