Cirrus Logic AN158 - Manual (Page 2)

AN158
2 AN158REV1
lized amplifier with has three low level input rang-
es (±25 mV, ±55 mV, and ±100 mV) and very low
input current. The amplifier’s input current is dy-
namic current (CVF current; for explanation of
CVF current, see the Summary) which is caused by
charge injection. Charge injection occurs due to in-
herent mismatch of the chopping switches in the
chopper circuitry of the amplifier.
The magnitude of the CVF current is a function of
the frequency used to operate the chopping switch-
es. The CS552x family has two bits in the configu-
ration register (Chop Frequency Select bits) which
allow the user to program the rate of the chopping
frequency, (i.e. the user can control the magnitude
of the input CVF current). When set for the lowest
chopping rate, the chop clock frequency is 256 Hz
when XIN = 32.768 kHz. Note that if the XIN clock
frequency is changed, the chop frequency scales
proportionally. At a chop clock rate of 256 Hz, the
CVF current of the PGIA inputs will be below
300 pA over the industrial temperature range. For
the 100 mV input range at 25 °C, this equates to an
input impedance of approximately 1000 M
Ω
(100 mV/ 100 pA).
Many competitors ADCs, which are “designed” for
low level signal measurement, exhibit CVF input
currents of 10-30 nA, or as much as 100 times high-
er. This current is typically not specified in the
datasheet.
MEASURING HIGH VOLTAGES
The very low CVF current on the ±100 mV and
lower ranges allows the use of fairly large source
impedances in front of the amplifier. This enables
this series of ADCs to use high impedance resistive
dividers in front of the ADC to divide down high
level input voltages.
Figure 3 illustrates an example of the ADC being
used with external divider resistors to achieve the
measurement of a ±10 V input signal. The input
current from the 10 V source will be about 10
µ
A
(10 V/ 10M
Ω
). The input current to the amplifier
will not exceed 300 pA over the industrial temper-
ature range if XIN = 32.768 kHz and the lowest
chop clock frequency (256 Hz) is used. The ratio of
these two currents is about 3333 to 1; therefore the
possible measurement error, due to the CVF cur-
rent, is approximately 1/3333 or about 0.03%. Fig-
ure 3 illustrates an alternative divider with less
initial error due to the CVF current, typically
0.003%. Note that errors caused by initial resistor
tolerances and by the initial CVF current can be re-
moved by using system calibration (refer to the
CS552x datasheet for more detail on system cali-
bration). Since these initial errors can be removed,
the residual error becomes a function of the resistor
tempco and the drift of the CVF current. Figure 4
illustrates an example of the measurement of a very
high voltage: 1,000 V dc. If very high voltages are
measured be certain the resistors have adequate
voltage breakdown capability and sufficient power
dissipation capability.
≈
1
µ
A F.S.
+ 10 V
100 k Ω
+ 300 pA max 10 M
Ω
300 pA
1
µ
A
= 0.03%
PGIA
+
-
NBV
PGIA set for ± 100 mV
-2.1 V
Figure 2. Resistor Divider for + 10 V Input
Figure 3. Alternate + 10 V Divider
PGIA
+
-
NBV
≈
10
µ
A F.S.
10 k
Ω
+ 300 pA max 1 M
Ω
300 pA
10
µ
A
= 0.003%
+ 10 V
PGIA set for ± 100 mV
-2.1 V