Cirrus Logic AN74 - Manual (Page 7)

AN74
AN74Rev2 7
/**************************************************************************************
* Program Code
**************************************************************************************
* Routine - Main
* Input
- none
* Output - none
* This is the entry point to the program
**************************************************************************************/
main() {
mode = 1; /*Make Communication be Four-Wire Mode*/
initialize(); /*Call Routine to Initialize 80C51 and CS5525/6/9*/
while(1){
command = 0x82; /*Prepare to Write to Gain Register*/
high_byte = 0x80; /*Make High_byte 80 (HEX)*/
mid_byte = 0x00; /*Make Mid_byte all Zero’s*/
low_byte = 0x00; /*Make low_byte all Zero’s*/
write_to_register(command,low_byte,mid_byte,high_byte);/*Write to gain Register*/
read_register(0x92);
/*Read Contents of Gain Register*/
while(1){
acquire_conversion(0xC0); /*Acquire a Single Conversion*/
}/*End inner while loop*/
}/*End While Loop*/
}/*end main*/
/*****************************Subroutines**********************************************/
/*************************************************************************************
* Routine - initialize
* Input
- none
* Output - none
* This subroutine initializes Port 1 for interfacing to the CS5525/6/9 ADC.
* It provides a time delay for oscillator start-up/wake-up period.
* A typical start-up time for a 32768 Hz crystal, due to high Q, is 500 ms.
* Also 1003 XIN clock cycles are allotted for the ADC's power on reset.
**************************************************************************************/
void initialize()
/*** Local Variables ***/
data int counter;
/*** Body of Subroutine ***/
/*** Initialize 80C51’s Port 1 ***/
P1
= 0xF4; /*SCLK - Output */
/*SDI
- Output */
/*SDO - Input */
/*CS
- Output */
/*Initialize CS5525/6/9*/
/*Delay 2048 SCLK Cycles, to allow time for Oscillator start-up and power on reset*/
for(counter=0;counter<2047;counter++){
SCLK = 0x01; /*Assert SCLK*/
SCLK = 0x00; /*Deassert*/
}