Cirrus Logic AN314 - Manual (Page 2)

2 AN314REV1
AN314
3. REQUIREMENTS FOR MULTIPLEXING THE CS556X/7X/8X
For higher-throughput in multiplexed applications, it is desirable for the converter to fully settle on each conversion.
In other words, the digital filter's output must accurately reflect the analog value on the input during the conversion.
Additionally, the input multiplexer and any buffer amplifiers must be settled to the full accuracy of the converter be-
fore the samples are taken. This requires both the converter and the analog input circuitry to be fast settling. This
is especially true if any amplifier or anti-aliasing resistor and capacitor is placed between the multiplexer and the
ADC as illustrated in
Figure 2 . With a multiplexer it is possible for the ADC input to see a full-scale change from one
conversion to the next. Any amplifier, or RC time constant due to resistance and capacitance, between the multi-
plexer and the ADC must fully settle to the new value before the sampling begins.
Figure 2. Amplifier and Filter between Multiplexer and ADC
With high-throughput converters like the 50 kSps CS5560/61, 100 kSps CS5570/71, or the 200 kSps CS5580/81
the circuit must settle in less than 10 MCLK periods (625 nanoseconds). The multiplexer before a SAR converter
can be switched to the next channel after the conversion begins since the signal has already been sampled. How-
ever, many SAR ADC data sheets warn that a certain "quiet" period should be observed to prevent coupling of noise.
The CS556x/7x/8x requires that the multiplexer be switched at the end of the conversion, since it is taking multiple
samples of the input signal during the conversion (see
Figure 3 ).
Figure 3. Multiplexer Timing Requirements
Therefore, an alternative should be considered where the amplifiers and anti-aliasing capacitors are on the input of
the multiplexer. This generally requires a multiplexer with very low “on” resistance but the benefits are that the am-
plifier(s) and RC networks do not have to settle from possible large step changes when the multiplexer switches to
another input.
Figure 4 illustrates this arrangement.
ADC
MUX
AIN1
AIN2
AIN3
AIN4
AMP
CONV
RDY
Switch MUX here
Analog Input must be settled here.
If CONV is held low , input must be
settled within 10 MCLKs after RDY falls.
See data sheet for specific timing
CS 5560/ 61 – 304 MCLKs
CS 5570/ 71 – 144 MCLKs
CS 5580/ 81 – 64 MCLKs