6 clock edge selection, 7 jitter attenuator selection, 8 loopback mode selection – Cirrus Logic CDB61880 User Manual

Page 7

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background image

CDB61880

DS450DB1

7

mitters in a high impedance state. Removing the
shorting block, enables the transmitters.

See

Figure 5.

2.6 Clock Edge Selection

In clock/data recovery mode, jumper J93 selects
the edge of RCLK and SCLK on which the
RPOS/RDATA, RNEG, and SDO data signals are
valid. When in data recovery mode, jumper J93 se-
lects the output polarity of RPOS/RNEG. The func-
tion of J93 applies to both the Hardware and Host
mode.

Figure 6

shows the settings for jumper J93

and the effect in both clock/data recovery and data
recovery only mode.

2.7 Jitter Attenuator Selection

In Hardware mode, switch S10 (JASEL) controls
the position of the jitter attenuator for all eight
channels. The corner frequency and FIFO length

can not be changed in Hardware mode.

Figure 7

shows the settings for switch S10.

In Host mode, switch S10 has no effect on the
CS61880 device and should be set to the open
(middle) position.

2.8 Loopback Mode Selection

In Hardware mode, the Loopback modes are con-
figured with switches S1 through S8 (0-7).

Figure 8

shows the three different settings for all eight loop
back switches.

In Host mode, switches S1 through S8 must be set
to the NONE (middle) position to allow host inter-
face control.

H I

LO

E n able all eight

transm itters

H i-Z all

eight transm itters

J2

3

TX

O

E

H I

LO

TX

O

E

J2

3

Figure 5. Transmitter Enable Selection

J93

H I

L O

Clock/Data Recovery -
R P O S / R N E G = f a l l i n g
e d g e R C L K S D O =
r i s i n g e d g e S C L K

Clock/Data Recovery -
R P O S / R N E G = r i s i n g
e d g e R C L K S D O =
f a l l i n g e d g e S C L K

Data Recovery -
R P O S / R N E G
polarity active high

Data Recovery -
R P O S / R N E G
polarity active low

CKLE

J93

H I

L O

CKLE

Figure 6. Clock Edge Selection

S 1 0

Hardware Mode

- JA placed in

transmit path

S 1 0

S 1 0

H I G H

O P E N

L O W

H I G H

O P E N

L O W

H I G H

O P E N

L O W

Hardware Mode

- JA Disabled

Hardware Mode

- JA placed in

receive path

J A S E L

J A S E L

J A S E L

Figure 7. Jitter Attenuator Selection

H a r d w a r e M o d e -

S e l e c t s R e m o t e

L o o p b a c k

H a r d w a r e M o d e -

Selects local

L o o p b a c k

H a r d w a r e M o d e -

Selects no

L o o p b a c k

0 - 7

0 - 7

0 - 7

S1 - S8

S1 - S8

S1 - S8

Lloop

none

Rloop

Lloop

none

Rloop

Lloop

none

Rloop

Figure 8. Loopback Mode Selection

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