6 layout guidelines, 1 cs6422-specific guidelines, 3 half-duplex alternate counting – Cirrus Logic AN168 User Manual

Page 25: Figure 18. suggested cs6422 layout, An168

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AN168

AN168REV2

25

1.5.4.3 Half-duplex alternate counting

The Half-duplex alternate counting test tests the
half-duplex behavior of the system. This test is
useful even if half-duplex mode is disabled,
because the half-duplex engine controls in part the
training of the adaptive filters.

In the Half-duplex alternate counting test, the
CS6422 is loaded with the recommended
configuration set, with the exception that ACC is
set to ‘cleared’, which prevents the echo canceler
from training and keeps the system in half-duplex.
HDD must be set to ‘0’ for this test.

In this test, the talkers alternate counting in
sequence. For example, the far-end says, “one”,
followed by the near-end saying, “two”, followed
by the far-end saying “three”, etc.

Each side listens for the expected count, and looks
for dropped counts. If the near-end environment is
noisy, it make take a few seconds for the
half-duplexor to begin switching properly.

Parameters that can be adjusted for this test are
HDly, THDet, RHDet, and RSThd. HDly controls

the delay between the system switching from
transmit mode to receive mode. RHDet and THDet
control the SNR level at which speech is detected.
Generally, RHDet and THDet should be equal;
however, if one end of the link is consistently cut
off, they may need to be imbalanced in order to
improve performance.

If there is a network sidetone, it is important that
the Network Echo Canceler be enabled during
half-duplex testing, otherwise the transmit path
may be cut off by its own network echo, causing
halted speech.

1.6 Layout Guidelines

This section contains guidelines regarding PCB
layout in CS6422 systems and car kits in particular.

1.6.1

CS6422-specific guidelines

1) All ground pins on the CS6422 should be refer-

enced to AGND (analog ground plane).

Signals should NOT be routed under the CS6422,
with the exception of the crystal oscillator signals
and the MB signal as shown in Fig. 18.

AGND

DVDD

MB

AVDD

+5V

Analog
Supply

DGND

From
Ferrite
Bead

CS6422

Figure 18. Suggested CS6422 Layout

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