Figure 4. i·c mode timing, Figure 4. i²c mode timing – Cirrus Logic CS8406 User Manual
Page 8
8
DS580F6
CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
13. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter
Symbol
Min
Typ
Max
Units
SCL Clock Frequency
fscl
-
-
100
kHz
Bus Free Time Between Transmissions
t
buf
4.7
-
-
s
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
-
s
Clock Low Time
t
low
4.7
-
-
s
Clock High Time
t
high
4.0
-
-
s
Setup Time for Repeated Start Condition
t
sust
4.7
-
-
s
SDA Hold Time from SCL Falling
t
hdd
0
-
-
s
SDA Setup Time to SCL Rising
t
sud
250
-
-
ns
Rise Time of Both SDA and SCL Lines
t
r
-
-
1000
ns
Fall Time of Both SDA and SCL Lines
t
f
-
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
-
s
t buf
t hdst
t hdst
t low
t r
t f
t hdd
t high
t sud
tsust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
Figure 4. I²C Mode Timing