4 jitter attenuation, Figure 21. revision a, Figure 22. revision a1 – Cirrus Logic CS8415A User Manual
Page 45: Figure 23. revision a2 using a1 values, Figure 24. revision a2 using a2* values, Figure 21, Figure 22, Figure 23, Figure 24, Cs8415a
DS470F4
45
CS8415A
15.3.4
Jitter Attenuation
Shown in
, and
are jitter attenuation plots for the various revi-
sions of the CS8415A when used with the appropriate external PLL component values (as noted in
). The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates
less than 32 kHz. These specifications state a maximum of 2 dB jitter gain or peaking.
10
−1
10
0
10
1
10
2
10
3
10
4
10
5
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
Jitter Attenuation (dB)
10
−1
10
0
10
1
10
2
10
3
10
4
10
5
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
Jitter Attenuation (dB)
10
−1
10
0
10
1
10
2
10
3
10
4
10
5
−25
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
Jitter Attenuation (dB)
10
−1
10
0
10
1
10
2
10
3
10
4
10
5
−25
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
Jitter Attenuation (dB)
Figure 21. Revision A
Figure 22. Revision A1
Figure 23. Revision A2 using A1 Values
Figure 24. Revision A2 using A2* Values