Figure 4. i·c mode timing, Figure 4. i²c mode timing – Cirrus Logic CS8416 User Manual
Page 11
DS578F3
11
CS8416
SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
Notes:
15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f
scl
-
100
kHz
Bus Free Time Between Transmissions
t
buf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
µs
Clock Low time
t
low
4.7
-
µs
Clock High Time
t
high
4.0
-
µs
Setup Time for Repeated Start Condition
t
sust
4.7
-
µs
SDA Hold Time from SCL Falling
t
hdd
10
-
ns
SDA Setup time to SCL Rising
t
sud
250
-
ns
Rise Time of SCL and SDA
t
r
-
1000
ns
Fall Time SCL and SDA
t
f
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
µs
t buf
t hdst
t hdst
t
low
t r
t f
t
hdd
t high
t sud
t sust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
Figure 4. I²C Mode Timing