Cirrus Logic CS8422 User Manual

Cs8422, Sample rate converter features, Digital audio interface receiver features

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Table of contents

Document Outline

Table of Contents
List of Figures
List of Tables
1. Pin Description
- 1.1 Software Mode
- 1.2 Hardware Mode
2. Characteristics and Specifications
3. Typical Connection Diagrams
- 3.1 Software Mode
- 3.2 Hardware Mode
4. Overview
5. Three-Wire Serial Input/Output Audio Port
- 5.1 Serial Port Clock Operation
6. Digital Interface Receiver
- 6.1 AES3 and S/PDIF Standards
- 6.2 Receiver Input Multiplexer
  - 6.2.1 Hardware Mode Control
  - 6.2.2 Software Mode Control
- 6.3 Recovered Master Clock - RMCK
  - 6.3.1 Hardware Mode Control
  - 6.3.2 Software Mode Control
- 6.4 XTI System Clock Mode
  - 6.4.1 Hardware Mode Control
  - 6.4.2 Software Mode Control
- 6.5 AES11 Behavior
- 6.6 Error and Status Reporting
  - 6.6.1 Software Mode
  - 6.6.2 Hardware Mode Control
- 6.7 Non-Audio Detection
  - 6.7.1 Hardware Mode Control
  - 6.7.2 Software Mode Control
- 6.8 Format Detection (Software Mode Only)
- 6.9 Interrupts (Software Mode Only)
- 6.10 Channel Status and User Data Handling
  - 6.10.1 Hardware Mode Control
  - 6.10.2 Software Mode Control
7. Sample Rate Converter (SRC)
- 7.1 SRC Data Resolution and Dither
  - 7.1.1 Hardware Mode Control
  - 7.1.2 Software Mode Control
- 7.2 SRC Locking
- 7.3 SRC Muting
- 7.4 SRC Master Clock
  - 7.4.1 Hardware Mode Control
  - 7.4.2 Software Mode Control
8. Hardware Mode Control
- 8.1 Hardware Mode Serial Audio Port Control
9. Software Mode Control
- 9.1 Control Port Description
10. Register Quick Reference
11. Software Register Bit Definitions
- 11.1 CS8422 I.D. and Version Register (01h)
- 11.2 Clock Control (02h)
- 11.3 Receiver Input Control (03h)
- 11.4 Receiver Data Control (04h)
- 11.5 GPO Control 1 (05h)
- 11.6 GPO Control 2 (06h)
- 11.7 Serial Audio Input Clock Control (07h)
- 11.8 SRC Output Serial Port Clock Control (08h)
- 11.9 Recovered Master Clock Ratio Control & Misc. (09h)
- 11.10 Data Routing Control(0Ah)
- 11.11 Serial Audio Input Data Format (0Bh)
- 11.12 Serial Audio Output Data Format - SDOUT1 (0Ch)
- 11.13 Serial Audio Output Data Format - SDOUT2 (0Dh)
- 11.14 Receiver Error Unmasking (0Eh)
- 11.15 Interrupt Unmasking (0Fh)
- 11.16 Interrupt Mode (10h)
- 11.17 Receiver Channel Status (11h)
- 11.18 Format Detect Status (12h)
- 11.19 Receiver Error (13h)
- 11.20 Interrupt Status (14h)
- 11.21 PLL Status (15h)
- 11.22 Receiver Status (16h)
- 11.23 Fs/XTI Ratio (17h - 18h)
- 11.24 Q-Channel Subcode (19h - 22h)
- 11.25 Channel Status Registers (23h - 2Ch)
- 11.26 IEC61937 PC/PD Burst preamble (2Dh - 30h)
12. Applications
- 12.1 Reset, Power Down, and Start-Up
- 12.2 Power Supply, Grounding, and PCB layout
- 12.3 External Receiver Components
  - 12.3.1 Attenuating Input signals
  - 12.3.2 Isolating Transformer Requirements
- 12.4 Channel Status Buffer Management
- 12.5 Jitter Attenuation
- 12.6 Jitter Tolerance
- 12.7 Group Delay
13. Performance Plots
14. Package Dimensions
15. Thermal Characteristics and Specifications
16. Ordering Information
17. References
18. Revision History