Cirrus Logic CDB8422 - Manual (Page 29)

DS692DB2 29
CDB8422
5. JUMPER SETTINGS
Note: All settings denoted by an asterisk (*) are the Default Factory Settings.
Note: If a S/PDIF source is connected to the board, the AES3/EBU jumpers (J21 and J29) should be unpop-
ulated to ensure proper operation. If an AES3/EBU source is connected to the board, the S/PDIF
jumpers (J4, J9, J14, and J18) should be unpopulated to ensure proper operation.
6. LEDS
JMP LABEL PURPOSE POSITION FUNCTION SELECTED
J20 [No Label]
Selects voltage source for the
CDB8422
1 - 2 Voltage source is USB connection (J37).
*2 - 3 Voltage source is +5 V binding post (J2).
J11
J8
J13
J17
DC0
DC1
DC2
DC3
Bypasses optical S/PDIF input DC
coupling capacitor
SHUNTED 0.01 µF series capacitor is shorted.
*OPEN 0.01 µF series capacitor in optical input path.
J4
J9
J14
J18
[No Label]
Selects S/PDIF input source to
receiver input pins of CS8422
*1 - 2 Optical S/PDIF input selected.
2 - 3 Coaxial S/PDIF input selected.
J23 [No Label]
Selects XTI clock source for
CS8422
1 - 2 Crystal Y2 selected.
*3 - 4 Oscillator Y1 selected.
5 - 6 MCLK from header J22 selected.
J31 CS8406/TX
Selects S/PDIF signal source for
J27 and J28
1 - 2 GPO2 S/PDIF pass through from CS8422 selected.
*2 - 3 CS8406 S/PDIF output selected.
J21
J29
DIFF IN SEL
Connects AES3/EBU signal from
J19 to receiver input pins of
CS8422
*RXP0/RXN0 RXP0/RXN0 input pair selected.
RXP1/RXN1 RXP1/RXN1 input pair selected.
Table 7. Jumper Settings
LED LABEL Hardware Mode Software Mode
D2 GPO2/NV_RERR NV/RERR (CS8422 pin 9) GPO2 (CS8422 pin 18)
D3 GPO0/V_AUDIO V/AUDIO (CS8422 pin 10) GPO0 (CS8422 pin 16)
D4 GPO1/SRC_UNLOCK SRC_UNLOCK (CS8422 pin 30) GPO1 (CS8422 pin 17)
D8 USB PRESENT USB power indicator USB power indicator
D14 DONE FPGA programming finished FPGA programming finished
D15 INIT FPGA programming initialized FPGA programming initialized
Table 8. LEDs