Cirrus Logic AN181 - Manual (Page 3)

AN181
AN181REV1 3
Typical Connection Diagram
EECS
EEDATAOUT
EESK
SA[10:19]
MEMW
MEMR
IOW
IOR
REFRESH
SBHE
SD[8:15]
INTRQ0
INTRQ1
RXD-
RXD+
TXD-
TXD+
DO-
DO+
CI-
CI+
DI-
DI+
LANLED
LINKLED
EEDATAIN
AEN
RESET
INTRQ2
INTRQ3
DMARQ0
DMACK0
DMARQ1
DMACK1
DMARQ2
DMACK2
MEMCS16
IOCHRDY
68 pF
1
3
6
8
24.9
Ω, 1%
24.9
Ω, 1%
92
91
88
87
100
Ω, 1%
RJ45
16
14
11
9
6
3
2
1
84
82
81
79
83
80
680
Ω
680
Ω
XTAL1 XTAL2 SLEEP TEST RES
3
5
4
6
28
62
61
29
7
8
10
97 98 93
4.99 k
Ω
, 1% 20 MHz
Vcc
4.7 k
Ω
CS8900
CHIPSEL
IOCS16
49
63
75
36
34
64
33
32
30
35
31
15
13
14
16
11
12
99
100
ELCS
10 BASE T
Isolation
Transformer
BSTATUS/HCI
Vcc
77 76
78
2 0.1 µF
7 0.1 µF
Vcc
SA[0:9]
10
SA[0:9]
IOW
IOR
SD[0:7]
8
CHIPSEL
RESET
SD[0:7]
A