Cirrus Logic EP7309 User Manual
Page 35

DS507F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
35
EP7309
High-Performance, Low-Power System on Chip
44
N1
nEXTFIQ
I
79
45
L5
PE[2]/CLKSEL
I/O
80
46
N2
PE[1]/BOOTSEL1
I/O
83
47
M4
PE[0]/BOOTSEL0
I/O
86
53
T2
PD[7]
I/O
89
54
T3
PD[6]
I/O
92
55
N5
PD[5]
I/O
95
56
R3
PD[4]
I/O
98
59
T4
PD[3]
I/O
101
60
N6
PD[2]
I/O
104
61
R4
PD[1]
I/O
107
62
L7
PD[0]/LEDFLSH
O
110
68
T6
SSIRXFR
I/O
122
69
K8
ADCIN
I
125
70
R6
nADCCS
O
126
75
M8
DRIVE1
I/O
128
76
T8
DRIVE0
I/O
131
77
N8
ADCCLK
O
134
78
R8
ADCOUT
O
136
79
N9
SMPCLK
O
138
80
T9
FB1
I
140
82
M9
FB0
I
141
83
R9
COL7
O
142
84
L9
COL6
O
144
85
T10
COL5
O
146
86
K9
COL4
O
148
87
R10
COL3
O
150
88
N10
COL2
O
152
91
R11
COL1
O
154
92
M10
COL0
O
156
93
T12
BUZ
O
158
94
L10
D[31]
I/O
160
95
R12
D[30]
I/O
163
96
N11
D[29]
I/O
166
97
T13
D[28]
I/O
169
99
R13
A[27]
Out
172
100
M11
D[27]
I/O
174
101
T14
A[26]
O
177
Table 21. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position